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| PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DESCRIPTION The M37754FFCGP and the M37754FFCHP are single-chip microcomputers designed with high-performance CMOS silicon gate technology, including the internal flash memory. These are housed in 100-pin plastic molded QFP. These microcomputers have a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing, and the bus interface unit enhances the memory access efficiency to execute instructions fast. In addition to the 7700 Family basic instructions, the M37754FFCGP and the M37754FFCHP have 6 special instructions which contain instructions for signed multiplication/division; these added instructions improve the servo arithmetic performance to control hard disk drives and so on. These microcomputers also include the flash memory, RAM, multiple-function timers, motor control function, serial I/O, A-D converter, D-A converter, and so on. The internal flash memory can be programed and erased by using a PROM programmer or by control of the central processing unit (CPU). Therefore, these microcomputers can change the program easily even after they are mounted on the board. APPLICATION Control devices for personal computer peripheral equipment such as CD-ROM drives, hard disk drives, high density FDD, printers Control devices for office equipment such as copiers and facsimiles Control devices for industrial equipment such as communication and measuring instruments Control devices for equipment required for motor control such as inverter air conditioner and general purpose inverter DISTINCTIVE FEATURES * * * * * * * * * * * * * * * * * * * 2 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR M37754FFCGP PIN CONFIGURATION (TOP VIEW) P87/TXD1 81 P86/RXD1 82 P85/CLK1 83 P84/CTS1/RTS1/DA1/INT4 84 P83/TXD0 85 P82/RXD0/CLKS0 86 P81/CLK0 87 P80/CTS0/RTS0/CLKS1/DA0 88 VCC 89 AVCC 90 VREF 91 AVSS 92 VSS 93 P77/AN7/ADTRG 94 P76/AN6 95 P75/AN5 96 P74/AN4 97 P73/AN3 98 P72/AN2 99 P71/AN1 100 SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Outline 100P6S-A M37754FFCGP P70/AN0 P95/INT3/KI4 P94/CS4/RTP13 P93/CS3/A22/RTP12 P92/CS2/A21/U/RTP11 P91/CS1/A20/V/RTP10 P90/CS0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN/W/RTP03 P52/TA1OUT/U/RTP02 P51/TA0IN/V/RTP01 P50/TA0OUT/W/RTP00 P47 P46 P45 P44 P43 P42/1 P41/RDY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P111/D9 P112/D10 P113/D11 P114/D12 P115/D13 P116/D14 P117/D15 P30/WR P31/BHE P32/ALE P33/HLDA VCC VSS E/RD XOUT XIN RESET CNVSS BYTE P40/HOLD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8 P11/A9 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/A16 P21/A17 P22/A18 P23/A19 P27/A23 P100/D0/LA0 P101/D1/LA1 P102/D2/LA2 P103/D3/LA3 P104/D4/LA4 P105/D5/LA5 P106/D6/LA6 P107/D7/LA7 P110/D8 MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION M37754FFCHP PIN CONFIGURATION (TOP VIEW) 75 P03/A3 74 P04/A4 73 P05/A5 72 P06/A6 71 P07/A7 70 P10/A8 69 P11/A9 68 P12/A10 67 P13/A11 66 P14/A12 65 P15/A13 64 P16/A14 63 P17/A15 62 P20/A16 61 P21/A17 60 P22/A18 59 P23/A19 58 P27/A23 57 P100/D0/LA0 56 P101/D1/LA1 55 P102/D2/LA2 54 P103/D3/LA3 53 P104/D4/LA4 52 P105/D5/LA5 51 P106/D6/LA6 P02/A2 76 P01/A1 77 P00/A0 78 P87/TXD1 79 P86/RXD1 80 P85/CLK1 81 P84/CTS1/RTS1/DA1/INT4 82 P83/TXD0 83 P82/RXD0/CLKS0 84 P81/CLK0 85 P80/CTS0/RTS0/CLKS1/DA0 86 87 VCC 88 AVCC VREF 89 90 AVSS 91 VSS P77/AN7/ADTRG 92 P76/AN6 93 P75/AN5 94 P74/AN4 95 P73/AN3 96 P72/AN2 97 P71/AN1 98 P70/AN0 99 P95/INT3/KI4 100 M37754FFCHP 50 P107/D7/LA7 49 P110/D8 48 P111/D9 47 P112/D10 46 P113/D11 45 P114/D12 44 P115/D13 43 P116/D14 42 P117/D15 41 P30/WR 40 P31/BHE 39 P32/ALE 38 P33/HLDA 37 VCC 36 VSS 35 E/RD 34 XOUT 33 XIN 32 RESET 31 CNVSS 30 BYTE 29 P40/HOLD 28 P41/RDY 27 P42/1 26 P43 P94/CS4/RTP13 1 P93/CS3/A22/RTP12 2 P92/CS2/A21/U/RTP11 3 P91/CS1/A20/V/RTP10 4 P90/CS0 5 P67/TB2IN 6 P66/TB1IN 7 P65/TB0IN 8 P64/INT2 9 P63/INT1 10 P62/INT0 11 P61/TA4IN 12 P60/TA4OUT 13 P57/TA3IN/KI3 14 P56/TA3OUT/KI2 15 P55/TA2IN/KI1 16 P54/TA2OUT/KI0 17 P53/TA1IN/W/RTP03 18 P52/TA1OUT/U/RTP02 19 P51/TA0IN/V/RTP01 20 P50/TA0OUT/W/RTP00 21 P47 22 P46 23 P45 24 P44 25 Outline 100P6Q-A 3 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Bus width select input BYTE Data Bus(Even) Data Bus(Odd) Input/Output port P0 Input/Output port P9 Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Input/Output port P11 Input/Output Input/Output Input/Output Input/Output port P3 port P2 port P1 port P10 P0 (8) P9(6) P8(8) P7(8) P6(8) P5(8) P4(8) P11(8) P10 (8) P3 (4) P2 (5) P1 (8) Data Buffer DBH(8) Data Buffer DBL(8) Reference voltage input VREF Instruction Register(8) Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q2(8) (5V) AVCC Address Bus (0V) AVSS Incrementer(24) D-A1 Converter(8) UART 1(9) Data Address Register DA(24) CNVSS (0V) VSS Incrementer/Decrementer(24) Program Counter PC(16) Program Bank Register PG(8) Data Bank Register DT(8) WatchdogTimer Timer TB2(16) Timer TB1(16) Timer TA1(16) Flash memory 120 Kbytes RAM 3968 Bytes (5V) VCC Input Buffer Register IB(16) Reset input RESET Timer TA4(16) Timer TA3(16) Timer TA2(16) Processor Status Register PS(11) Direct Page Register DPR(16) Stack Pointer S(16) Index Register Y(16) Clock output Enable output XOUT E Index Register X(16) Clock Generating Circuit Accumulator B(16) Accumulator A(16) BLOCK DIAGRAM 4 Clock input XIN Arithmetic Logic Unit(16) Timer TA0(16) Timer TB0(16) UART 0(9) A-D Converter(10) D-A0 Converter(8) Program Address Register PA(24) PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION FUNCTIONS (Microcomputer mode) Parameter Number of basic machine instructions Instruction execution time Flash memory Memory size RAM P0, P1, P4-P8, P10, P11 P2 Input/Output ports P3 P9 TA0, TA1, TA2, TA3, TA4 Multiple-function timers TB0, TB1, TB2 Serial I/O A-D converter D-A converter Watchdog timer Dead-time timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Memory expansion Operating temperature range Device structure Package Input/Output withstand voltage Output current Functions 109 (103 basic instructions of 7700 Family + 6 special instructions) 100 ns (the fastest instruction at external clock 40 MHz frequency) 120 Kbytes 3968 bytes 8-bit x 9 5-bit x 1 4-bit x 1 6-bit x 1 16-bit x 5 16-bit x 3 (UART or clock synchronous serial I/O) x 2 10-bit x 1(8 channels) 8-bit x 2 12-bit x 1 8-bit x 3 5 external types, 16 internal types (Each interrupt can be set to priority levels 0 - 7.) Built-in (externally connected to a ceramic resonator or quartz crystal resonator) 5 V10 % 125 mW (at external clock 40 MHz frequency) 5V 5 mA Maximum 16 Mbytes -20 to 85 C CMOS high-performance silicon gate process 100-pin plastic molded QFP FUNCTIONS (Flash memory mode) Parameter Supply voltage Program/Erase voltage Flash memory mode Parallel I/O mode Serial I/O mode CPU reprogramming mode Parallel I/O mode Serial I/O mode CPU reprogramming mode Program/Erase control method Command number Parallel I/O mode Serial IO mode CPU reprogramming mode Functions 5 V 10 % 12 V 5 % 3 modes (parallel I/O, serial I/O, CPU reprogramming) Programming in unit of byte/120 Kbytes Programming in unit of byte/120 Kbytes Programming in unit of byte/112 Kbytes Batch erasing/120 Kbytes Batch erasing/120 Kbytes Batch erasing/112 Kbytes or 2-division-block erasing 2-division-block erasing: 56-Kbyte area to be erased is selectable. Program/Erase control by software command 7 commands 7 commands 7 commands 100 Programming method Erasing method Number of times for Program/Erase 5 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PIN DESCRIPTION (MICROCOMPUTER MODE) Pin VCC, VSS CNVSS _____ Name Power supply CNVSS input Reset input Clock input Clock output Enable output Input/ Output Input Input Input Output Output Functions Supply 5 V10 % to VCC and 0 V to VSS. This pin controls the processor mode. Connect to VSS for single-chip mode or memory expansion mode. Connect to VCC for microprocessor mode. This is reset input pin. The microcomputer is reset when supplying "L" level to this pin. These are I/O pins of internal clock generating circuit. Connect a ceramic or quartzcrystal resonator between XIN and XOUT. When an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. __ This pin outputs enable signal E, which indicates access state of data bus for single-chip mode. ___ This pin outputs RD signal for memory expansion mode or microprocessor mode. This pin determines whether the external data bus is 8-bit width or 16-bit width for memory expansion mode or microprocessor mode. The width is 16 bits when "L" signal inputs and 8 bits when "H" signal inputs. Power supply for the A-D converter and the D-A converter. Connect AVCC to VCC and AVSS to VSS externally. This is reference voltage input pin for the A-D converter and the D-A converter. In single-chip mode, port P0 is an 8-bit I/O port. This port has an I/O direction register and each pin can be programmed for input or output. These ports are in the input mode when reset. Address (A0 - A7) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. Address (A8 A15) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. Address (A16 A19, A23) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. In memory ___ ____ _____ expansion mode or microprocessor mode, WR, BHE, ALE, and HLDA signals are output. In single-chip mode, these pins have the same functions as port P0. In_____ memory expansion mode or microprocessor mode, P40, P41, and P42 become HOLD and ____ RDY input pins, and clock 1 output pin respectively. Functions of other pins are the same as in single-chip mode. In memory expansion mode, P42 can be programmed as I/O port. In addition to having the same functions as port P0 in single-chip mode, these pins also function as I/O pins for timer A0, timer A1, timer A2, timer A3, output pins for motor drive waveform, and input pins for key input interrupt. In addition to having the same functions as port P0 in single-chip mode, these pins ____ also ____function as I/O pins for timer A4, input pins for external interrupt input INT0, ____ INT1, and INT2, and input pins for timer B0, timer B1, and timer B2. In addition to having the same functions as port P0 in single-chip mode, these pins also function as input pins for A-D converter. In addition to having the same functions as port P0 in single-chip mode, these pins also function as I/O pins for UART0, UART1, output pins for D-A converter, and ____ input pin for INT4. In addition to having the same functions as port P0 in single-chip mode, these pins ___ also function as input pin for INT3, output pins for motor drive waveform. In memory expansion mode and microprocessor mode, these pins can be ___ ___ programmed as address (A20 - A22) or output pins for CS0 - CS4 RESET XIN XOUT __ E BYTE (Note) AVCC, AVSS VREF P00-P07 Bus width select input Input Analog supply input Reference voltage input I/O port P0 Input I/O P10-P17 P20-P23, P27 P30-P33 I/O port P1 I/O port P2 I/O port P3 I/O I/O I/O P40-P47 I/O port P4 I/O P50-P57 I/O port P5 I/O P60-P67 I/O port P6 I/O P70-P77 P80-P87 I/O port P7 I/O port P8 I/O I/O P90-P95 I/O port P9 I/O Note: It is impossible to change the input level of the BYTE pin in each bus cycle. In other words, bus width cannot be switched dynamically. Fix the input level of the BYTE pin to "H" or "L" according to the bus width used. 6 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Pin Name P100-P107 I/O port P10 Input/ Output I/O Functions In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, these pins become data I/O pins and operate as follows: (1) When using 16-bit width as external data bus width: Accessing external memory * * (2) When using 8-bit width as external data bus width: Accessing external memory * * P110-P117 I/O port P11 I/O In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, these pins operate as follows: (1) When using 16-bit width as external data bus width Accessing external memory * * 7 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PIN DESCRIPTION (FLASH MEMORY PARALLEL I/O MODE) Pin VCC, VSS CNVSS BYTE _____ RESET XIN XOUT _ E AVCC, AVSS VREF P00-P07 P10-P17 P20-P23, P27 P30-P33 P40-P47 P50-P57 P60-P67 P70-P77 P80-P87 P90-P95 P100-P107 P110-P117 Name Power supply VPP input Bus width select input Reset input Clock input Clock output Enable output Analog supply input Reference voltage input Address input (A0-A7) Address input (A8-A15) Input port P2 Input port P3 Input port P4 Control signal input Input port P6 Input port P7 Input port P8 Input port P9 Data I/O (D0-D7) Input port P11 Input /Output -- Input Input Input Input Output Output -- Input Input Input Input Input Input Input Input Input Input Input I/O Input Functions Supply 5 V 10 % to VCC and 0 V to VSS. Connect to 5 V 10 % in read-only mode, connect to 12 V 5 % in read/write mode. Connect to VSS. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. Keep it open. Connect AVCC to VCC and AVSS to VSS. Connect to VSS. Port P0 functions as 8-bit address input (A0-A7). Port P1 functions as 8-bit address input (A8-A15). Connect to VSS. Connect to VSS. Keep P42 open. Connect P40, P41, P43-P47 to VSS. ___ __ __ P50, P51 and P52 function as the WE, OE and CE input pins respectively. P54 functions as the A16 input pin. Connect P53 to VCC. Connect P55, P56 and P57 to VSS. Connect to VSS. Connect to VSS. Connect to VSS. Connect to VSS. Function as 8-bit data's I/O pins (D0-D7). Connect to Vss. 8 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE) Pin VCC, VSS CNVSS BYTE _____ RESET XIN XOUT _ E AVCC, AVSS VREF P00-P07 P10-P17 P20-P23, P27 P30-P33 P40-P43, P47 P44 P45 P46 P50, P52-P57 P51 P60-P67 P70-P77 P80-P87 P90-P95 P100-P107 P110-P117 Name Power supply VPP input Bus width select input Reset input Clock input Clock output Enable output Analog supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 BUSY output SDA I/O SCLK input Input port P5 Control signal input Input port P6 Input port P7 Input port P8 Input port P9 Input port P10 Input port P11 Input /Output -- Input Input Input Input Output Output -- Input Input Input Input Input Input Output I/O Input Input Input Input Input Input Input Input Input Functions Supply 5 V 10 % to VCC and 0 V to VSS. Connect to 12 V 5 %. Connect to VSS or VCC. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. "H" is output. Connect AVCC to VCC and AVSS to VSS. Input an arbitrary level between the range of VSS and VCC. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L" to P40, P41, P43, P47, or keep them open. Keep P42 open. This pin is for BUSY signal output. This pin is for serial data I/O. This pin is for serial clock input. Input "H" or "L", or keep them open. __ OE input pin Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. Input "H" or "L", or keep them open. 9 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION BASIC FUNCTION BLOCKS The M37754FFCGP and the M37754FFCHP have the same functions as the M37754M8C-XXXGP and the M37754M8C-XXXHP except for the following. Therefore, refer to the section on the M37754M8C-XXXGP and the M37754M8C-XXXHP. (1) Flash memory is included instead of ROM. (2) The memory size is different. (3) The memory area modification function is different. (4) Part of the peripheral devices control registers is different. (Flash memory control register, flash command register, and bits 3, 4 of particular function select register 0 are added.) MEMORY The memory map is shown in Figure 1. Bank 016 Bank 116 ************* Bank FE16 Bank FF16 00000016 00000016 00007F16 00008016 Internal RAM 3968 bytes 00000016 Peripheral devices control registers (Refer to Fig.2.) 00007F16 00FFFF16 01000016 000FFF16 00100016 Interrupt vector table 00FFD216 01FFFF16 Internal flash memory 120 Kbytes 00EFFF16 00FFD216 00FFFF16 01000016 010FFF16 INT4 INT3 A-D conversion UART1 transmission UART1 receive UART0 transmission UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 INT1 INT0 Watchdog timer DBC BRKinstruction 0 divide RESET 00FFFE16 FE000016 FEFFFF16 FF000016 01EFFF16 FFFFFF16 01FFFF16 Reserved area : The flash memory area (8 Kbytes) where it is impossible to erase/modify in the CPU reprogramming mode. (It is possible to erase/modify in the parallel I/O mode or the serial I/O mode.) Note: The internal memory area can be changed. (Refer to the section on the memory area modification function.) Fig. 1 Memory map 10 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som IN LIM E ARY MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Address (Hexadecimal notation) 000000 000001 Port P0 register 000002 Port P1 register 000003 000004 Port P0 direction register 000005 Port P1 direction register 000006 Port P2 register 000007 Port P3 register 000008 Port P2 direction register 000009 Port P3 direction register Port P4 register 00000A Port P5 register 00000B Port P4 direction register 00000C Port P5 direction register 00000D Port P6 register 00000E Port P7 register 00000F Port P6 direction register 000010 Port P7 direction register 000011 Port P8 register 000012 Port P9 register 000013 Port P8 direction register 000014 Port P9 direction register 000015 Port P10 register 000016 Port P11 register 000017 000018 Port P10 direction register Port P11 direction register 000019 00001A Waveform output mode register 00001B Dead-time timer 00001C Pulse output data register 1 Pulse output data register 0 00001D A-D control register 0 00001E A-D control register 1 00001F 000020 A-D register 0 000021 000022 A-D register 1 000023 000024 A-D register 2 000025 000026 A-D register 3 000027 000028 A-D register 4 000029 00002A A-D register 5 00002B 00002C A-D register 6 00002D 00002E A-D register 7 00002F UART0 transmit/receive mode register 000030 UART0 baud rate register 000031 000032 UART0 transmit buffer register 000033 UART0 transmit/receive control register 0 000034 UART0 transmit/receive control register 1 000035 000036 UART0 receive buffer register 000037 UART1 transmit/receive mode register 000038 UART1 baud rate register 000039 00003A UART1 transmit buffer register 00003B UART1 transmit/receive control register 0 00003C UART1 transmit/receive control register 1 00003D 00003E UART1 receive buffer register 00003F Address (Hexadecimal notation) Count start register 000040 000041 One-shot start register 000042 000043 Up-down register 000044 000045 Timer A write register 000046 Timer A0 register 000047 000048 Timer A1 register 000049 00004A Timer A2 register 00004B 00004C Timer A3 register 00004D 00004E Timer A4 register 00004F 000050 Timer B0 register 000051 000052 Timer B1 register 000053 000054 Timer B2 register 000055 Timer A0 mode register 000056 Timer A1 mode register 000057 Timer A2 mode register 000058 Timer A3 mode register 000059 Timer A4 mode register 00005A Timer B0 mode register 00005B Timer B1 mode register 00005C Timer B2 mode register 00005D Processor mode register 0 00005E Processor mode register 1 00005F Watchdog timer register 000060 Watchdog timer frequency select regsiter 000061 Chip select control register 000062 Chip select area register 000063 Comparator function select register 000064 Flash command register 000065 Comparator result register 000066 Flash memory control register 000067 D-A register 0 000068 000069 D-A register 1 00006A 00006B Particular function select register 0 00006C Particular function select register 1 00006D INT4 interrupt control register 00006E INT3 interrupt control register 00006F A-D interrupt control register 000070 UART0 trasmit interrupt control register 000071 UART0 receive interrupt control register 000072 UART1 trasmit interrupt control register 000073 UART1 receive interrupt control register 000074 Timer A0 interrupt control register 000075 Timer A1 interrupt control register 000076 Timer A2 interrupt control register 000077 Timer A3 interrupt control register 000078 Timer A4 interrupt control register 000079 Timer B0 interrupt control register 00007A Timer B1 interrupt control register 00007B Timer B2 interrupt control register 00007C INT0 interrupt control register 00007D INT1 interrupt control register 00007E INT2 interrupt control register 00007F Fig. 2 Location of peripheral devices and interrupt control registers 11 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som IN LIM E ARY MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Address Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Port P9 direction register Port P10 direction register Port P11 direction register Waveform output mode register Pulse output data register 1 Pulse output data register 0 A-D control register 0 A-D control register 1 UART 0 transmit/receive mode register UART 1 transmit/receive mode register UART 0 transmit/receive control register 0 UART 1 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 1 transmit/receive control register 1 Count start register One-shot start register Up-down register Timer A write register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 (0416)*** (0516)*** (0816)*** 0 (0916)*** (0C16)*** (0D16)*** (1016)*** (1116)*** (1416)*** (1516)*** (1816)*** (1916)*** (1A16)*** (1C16)*** (1D16)*** 0 0 0 0016 0016 0000 0000 0016 0016 0016 0016 0016 000000 0016 0016 0016 0016 0000 Watchdog timer Watchdog timer frequency select register Chip select control register Chip select area register Comparator function select register Comparator result register Flash memory control register D-A register 0 D-A register 1 Particular function select register 0 Particular function select register 1 INT4 interrupt control register INT3 interrupt control register A-D interrupt control register UART 0 transmit interrupt control register UART 0 receive interrupt control register UART 1 transmit interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Processor status register PS Program bank register PG Program counter PCH Program counter PCL Direct page register DPR Data bank register DT Address (6016)*** (6116)*** FFF16 00 (6216)*** 0 0 0 0 0 0 0 0 (6316)*** 0 0 0 (6416)*** (6616)*** (6716)*** (6816)*** (6A16)*** (6C16)*** (6D16)*** (6E16)*** 0016 0016 0000000 0016 0016 0016 0016 000000 000 (6F16)*** 0 0 0 0 0 0 0 0 (7016)*** (7116)*** (7216)*** (7316)*** (7416)*** (7516)*** (7616)*** (7716)*** (7816)*** (7916)*** (7A16)*** (7B16)*** (7C16)*** (7D16)*** (7E16)*** (7F16)*** ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 (1E16)*** 0 0 0 0 0 ? ? ? (1F16)*** 0 0 0 0 0 0 1 1 (3016)*** (3816)*** (3416)*** 0 (3C16)*** 0 0016 0016 01000 01000 (3516)*** 0 0 0 0 0 0 1 0 (3D16)*** 0 0 0 0 0 0 1 0 (4016)*** (4216)*** 0016 00000 (4416)*** 0 0 0 0 0 0 0 0 (4516)*** (5616)*** (5716)*** (5816)*** (5916)*** (5A16)*** (5B16)*** 0 0 1 (5C16)*** 0 0 1 (5D16)*** 0 0 1 0016 0016 0016 0016 0016 0000 0000 0000 000 000??0001?? 0016 Contents of FFFF16 Contents of FFFE16 000016 0016 (5E16)*** 0 0 0 0 0 0 0 0 (5F16)*** 0016 Contents of other registers and RAM are not initiallzed and must be initiallzed by software. Note : Bit 0 of chip select control register (address 6216) becomes "0" when CNVss pin level is "L"; that bit becomes "1" when the pin level is "H". Fig. 3 Microcomputer internal registers status after reset 12 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MEMORY AREA MODIFICATION FUNCTION For the M37754FFCGP and the M37754FFCHP, the internal memory's size and address area can be changed by setting bits 2, 3, 4 (memory allocation select bits) of the particular function select register 0 (see figure 5). Figure 4 shows the memory map when changing the internal memory area. ML0 : Memory allocation select bit 0 ML1 : Memory allocation select bit 1 ML2 : Memory allocation select bit 2 Note: The internal flash memory area becomes the external memory area in the microprocessor mode. (ML2, ML1, ML0) = (0, 0, 0) (ML2, ML1, ML0) = (0, 0, 1) Flash memory size : 120 Kbytes Flash memory size : 92 Kbytes RAM size : 3968 bytes RAM size : 3968 bytes 00 000016 00 000016 SFR SFR 00 008016 00 008016 Internal RAM 3968 bytes Internal RAM 3968 bytes 00 0FFF16 00 0FFF16 00 100016 External memory area 01 EFFF16 01 FFFF16 FF FFFF16 (ML2, ML1, ML0) = (1, 1, 1) (ML2, ML1, ML0) = (1, 0, 0) (ML2, ML1, ML0) = (1, 0, 1) (ML2, ML1, ML0) = (1, 1, 0) Flash memory size : 48 Kbytes Flash memory size : 32 Kbytes Flash memory size : 60 Kbytes Flash memory size : 56 Kbytes RAM size : 2048 bytes RAM size : 2048 bytes RAM size : 2048 bytes RAM size : 2048 bytes 00 000016 00 000016 00 000016 00 000016 SFR SFR SFR SFR 00 008016 Internal RAM 2048 bytes 00 008016 00 008016 Internal RAM 2048 bytes 00 008016 Internal RAM 2048 bytes Internal RAM 2048 bytes 00 087F16 00 087F16 00 087F16 00 087F16 External memory area 00 100016 External memory area 00 200016 00 400016 00 FFFF16 FF FFFF16 Fig. 4 Memory allocation (Internal memory area modification by memory allocation select bits) ,,, ,,,,,, ,,, ,,, ,,,,,, ,,,,,, ,,, ,,,,, ,,,,,, ,,,,, ,,, ,,,,, ,,,,,, ,,, ,,,,,, ,,,,, ,,,,,, ,,,,, ,,,,,, ,,, ,,,,, ,,,,,, ,, (ML2, ML1, ML0) = (0, 1, 0) Flash memory size : 60 Kbytes RAM size : 3072 bytes SFR Internal RAM 3072 bytes (ML2, ML1, ML0) = (0, 1, 1) Flash memory size : 56 Kbytes RAM size : 3072 bytes SFR Internal RAM 3072 bytes 00 000016 00 008016 00 0C7F16 00 100016 00 000016 00 008016 00 0C7F16 00 200016 00 800016 Internal flash memory 60 Kbytes Internal flash memory 56 Kbytes Internal flash memory 120 Kbytes 00 FFFF16 00 FFFF16 Internal flash memory 92 Kbytes External memory area External memory area (Reserved area) 01 EFFF16 01 FFFF16 (Reserved area) External memory area External memory area FF FFFF16 FF FFFF16 FF FFFF16 Internal flash memory 48 Kbytes 00 800016 Internal flash memory 60 Kbytes Internal flash memory 32 Kbytes Internal flash memory 56 Kbytes 00 FFFF16 00 FFFF16 00 FFFF16 External memory area External memory area External memory area External memory area FF FFFF16 FF FFFF16 FF FFFF16 13 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION 7 6 5 4 3 2 1 0 0 Particular function select register 0 Fix to "0" Address 6C16 External clock input select bit (Notes 1, 2) 0 : Actuated oscillation circuit; connecting resonator 1 : Stopped oscillation circuit; inputting externaly genarated clock Memory allocation select bits 2, 1, 0 (Note 2) 0 0 0 : ROM 120 Kbytes, RAM 3968 bytes (ROM : 00100016 to 1EFFFF16, RAM : 00008016 to 000FFF16) 0 0 1 : ROM 92 Kbytes, RAM 3968 bytes (ROM:00800016 to 01EFFF16, RAM:00008016 to 000FFF16) 0 1 0 : ROM 60 Kbytes, RAM 3072 bytes (ROM : 00100016 to 00FFFF16, RAM : 00008016 to 000C7F16) 0 1 1 : ROM 56 Kbytes, RAM 3072 bytes (ROM:00200016 to 00FFFF16, RAM:00008016 to 000C7F16) 1 0 0 : ROM 48 Kbytes, RAM 2048 bytes (ROM : 00400016 to 00FFFF16, RAM : 00008016 to 00087F16) 1 0 1 : ROM 32 Kbytes, RAM 2048 bytes (ROM:00800016 to 00FFFF16, RAM:00008016 to 00087F16) 1 1 0 : ROM 60 Kbytes, RAM 2048 bytes (ROM : 00100016 to 00FFFF16, RAM : 00008016 to 00087F16) 1 1 1 : ROM 56 Kbytes, RAM 2048 bytes (ROM:00200016 to 00FFFF16, RAM:00008016 to 00087F16) Standby state select bit 0 (Notes 1, 3) ; when WIT or STP instruction is executed in memory expansion or microprocessor mode 0 : Pins P0 to P3, P10, and P11 are for external data bus. 1 : Pins P0 to P3, P10, and P11 are for port output or port input. Standby state select bit 1 (Notes 1, 4) ; in execution of WIT or STP instruction 0 : "H" or "L" output for pins E/RD, WR 1 : "H" output for pins E/RD, WR STP return select bit 0 : Watchdog timer is used when returning from Stop mode 1 : Watchdog timer is not used when returning from Stop mode ; the microcomputer returns at once. Notes 1 : After the expansion function select bit (bit 5 of particular function select register 1; Figure 62) is "1", bits 1, 5 and 6 can be rewritten. 2 : To set bits 1 to 4, continuous-twice-write operation must be performed to address 6C16. 3 : When BYTE = "H" (8-bit external bus width), P11 becomes an input/output port independent of bit 5's contents. 4 : When the signal output disable select bit is "1" and bit 5 is "1", the E/RD pin always outputs "L" independent of bit 6's contents in execution of WIT or STP instruction. Fig. 5 Particular function select register 0 bit configuration 14 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION FLASH MEMORY MODE The M37754FFCGP and the M37754FFCHP have the flash memory mode in addition to the normal operation mode (microcomputer mode). The user can use this mode to perform read, program, and erase operations for the internal flash memory. The M37754FFCGP and the M37754FFCHP have three modes the user can choose: the parallel input/output and serial input/output mode, where the flash memory is handled by using the external programmer, and the CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). The following explains these modes. Functional outline (Parallel input/output mode) In the parallel input/output mode, the M37754FFCGP and the M37754FFCHP allows the user to choose an operation mode between the read-only mode and the read/write mode (software command control mode) depending on the voltage applied to the VPP pin. When VPP = VPPL, the read-only mode is selected, and the user can choose one of three states (e.g., read, output disable, or standby) de___ ___ ___ pending on inputs to the CE, OE, and WE pins. When VPP = VPPH, the read/write mode is selected, and the user can choose one of four states (e.g.,__ __ read, output ___ disable, standby, or write) depending on inputs to the CE, OE, and WE pins. Table 2 shows assignment states of control input and each state. Flash memory mode 1 (parallel I/O mode) The parallel I/O mode can be selected by connecting wires as shown in Figures 6, 7 and supplying power to the VCC and VPP pins. In this mode, the M37754FFCGP and the M37754FFCHP operate as an equivalent of MITSUBISHI's CMOS flash memory M5M28F101. However, because the M37754FFCGP and the M37754FFCHP's internal memory has a capacity of 120 Kbytes, programming is available for addresses 0100016 to 1EFFF16, and make sure that the data in addresses 0000016 to 00FFF16 and addresses 1F00016 to 1FFFF16 are FF16. Note also that the M37754FFCGP and the M37754FFCHP does not contain a facility to read out a device identification code by applying a high voltage to address input (A9). Be careful not to erratically set program conditions when using a general-purpose PROM programmer. Table 1 shows the pin assignments when operating in the parallel input/output mode. Read __ __ The microcomputer enters the read state by driving the CE, and OE ___ pins low and the WE pin high; and the contents of memory corresponding to the address to be input to address input pins (A0-A16). are output to the data input/output pins (D0-D7). Output disable __ The microcomputer enters the output disable state by driving the CE ___ __ pin low and the WE and OE pins high; and the data input/output pins enter the floating state. Standby __ The microcomputer enters the standby state by driving the CE pin high. The M37754FFCGP and the M37754FFCHP are placed in a power-down state consuming only a minimal supply current. At this time, the data input/output pins enter the floating state. Table 1. Pin assignments of M37754FFCGP and M37754FFCHP when operating in the parallel input/output mode VCC VPP VSS Address input Data I/O __ CE ___ OE ___ WE M37754FFCGP/CHP VCC CNVSS VSS Ports P0, P1, P54 Port P10 P52 P51 P50 M5M28F101 VCC VPP VSS A0-A16 D0-D7 __ CE __ OE ___ WE Write The microcomputer enters the write state by driving the VPP pin high ___ __ (VPP__ VPPH) and then the WE pin low when the CE pin is low and = the OE pin is high. In this state, software commands can be input from the data input/output pins, and the user can choose program or erase operation depending on the contents of this software command. Table 2. Assignment sates of control input and each state Pin Mode Read-only State Read Output disable Standby Read Output disable Standby Write __ __ ___ CE VIL VIL VIH VIL VIL VIH VIL OE VIL VIH x VIL VIH x VIH WE VIH VIH x VIH VIH x VIL VPP VPPL VPPL VPPL VPPH VPPH VPPH VPPH Data I/O Output Floating Floating Output Floating Floating Input Read/Write Note: x can be VIL or VIH. 15 PR ge. ion. icat to chan ecif l sp ubject a a fin es not mits ar li is is : Th metric ice Not e para Som I LIM E Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VCC P87 P86 P85 P84 P83 P82 P81 P80 VCC AVCC VREF AVSS VSS P77 P76 P75 P74 P73 P72 P71 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P27 P100 P101 P102 P103 P104 P105 P106 P107 P110 D0 D1 D2 D3 D4 D5 D6 D7 M37754FFCGP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P111 P112 P113 P114 P115 P116 P117 P30 P31 P32 P33 VCC VSS E XOUT XIN RESET CNVSS BYTE P40 VSS V VPP A16 WE OE CE P70 P95 P94 P93 P92 P91 P90 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 V : Connect to the ceramic oscillation circuit. indicates the flash memory pin. Outline 100P6S-A Fig. 6 Pin connection of M37754FFCGP when operating in parallel input/output mode 16 PR ge. ion. icat to chan ecif l sp ubject a a fin es not mits ar li is is : Th metric ice Not e para Som I LIM E Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P27 P100 P101 P102 P103 P104 P105 P106 D0 D1 D2 D3 D4 D5 D6 A2 A1 A0 VCC P02 P01 P00 P87 P86 P85 P84 P83 P82 P81 P80 VCC AVCC VREF AVSS VSS P77 P76 P75 P74 P73 P72 P71 P70 P95 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 M37754FFCHP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P107 P110 P111 P112 P113 P114 P115 P116 P117 P30 P31 P32 P33 VCC VSS E XOUT XIN RESET CNVSS BYTE P40 P41 P42 P43 D7 VSS V VPP A16 CE OE WE P94 P93 P92 P91 P90 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 V : Connect to the ceramic oscillation circuit. Outline 100P6Q-A Fig. 7 Pin connection of M37754FFCHP when operating in parallel input/output mode indicates the flash memory pin. 17 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Read-only mode The microcomputer enters the read-only mode by applying VPPL to the VPP pin. In this mode, the user can input the address of a memory location to be read and the control signals at the timing shown in Figure 8, and the M37754FFCGP and the M37754FFCHP will output the contents of the user's specified address from data I/O pin to the external. In this mode, the user cannot perform any operation other than read. VIH Address VIL tRC VIH CE VIL ta(CE) VIH OE VIL VIH WE VIL VOH Data VOL Floating ta(OE) tOLZ tCLZ ta(AD) Dout tDH Floating tWRR tDF Valid address Fig. 8 Read timing Read/Write mode The microcomputer enters the read/write mode by applying VPPH to the VPP pin. In this mode, the user must first input a software command to choose the operation (e. g., read, program, or erase) to be performed on the flash memory (this is called the first cycle), and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called the second cycle). When this is done, the M37754FFCGP and the M37754FFCHP execute the specified operation. Table 3. Software command (Parallel input/output mode) Symbol Read Program Program verify Erase Erase verify Reset Device identification First cycle Address input x x x x Verify address x x Table 3 shows the software commands and the input/output information in the first and the second cycles. The input address is latched ___ internally at the falling edge of the WE input; software commands and other input data are latched internally at the rising edge of the ___ WE input. The following explains each software command. Refer to Figures 9 to 11 for details about the signal input/output timings. Data input 0016 4016 C016 2016 A016 FF16 9016 Second cycle Address input Data I/O Read address Read data (Output) Program address Program data (Input) x Verify data (Output) x 2016 (Input) x Verify data (Output) x FF16 (Input) ADI DDI (Output) Note: ADI = Device identification address : manufacturer's code 0000016, device code 0000116 DDI = Device identification data : manufacturer's code 1C16, device code D016 X can be VIL or VIH. 18 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Read command The microcomputer enters the read mode by inputting command code "0016" in the first cycle. The command code is latched into the ___ internal command latch at the rising edge of the WE input. When the address of a memory location to be read is input in the second cycle, with control signals input at the timing shown in Figure 9, the M37754FFCGP and the M37754FFCHP output the contents of the specified address from the data I/O pins to the external. The read mode is retained until any other command is latched into the command latch. Consequently, once the M37754FFCGP and the M37754FFCHP enter the read mode, the user can read out the successive memory contents simply by changing the input address and executing the second cycle only. Any command other than the read command must be input beginning from its command code over again each time the user execute it. The contents of the command latch immediately after power-on is 0016. VIH Address VIL tWC VIH CE VIL tCS VIH OE VIL tRRW VIH WE VIL ta(OE) tDS VIH Data VIL tVSC VPPH VPP VPPL 0016 tDH tOLZ tCLZ ta(AD) Dout tDH tWP tWRR tDF tCH ta(CE) tRC Valid address Fig. 9 Timings during reading 19 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Program command The microcomputer enters the program mode by inputting command code "4016" in the first cycle. The command code is latched into the ___ internal command latch at the rising edge of the WE input. When the address which indicates a program location and data are input in the second cycle, the M37754FFCGP and the ___ M37754FFCHP internally latch the address at the falling edge of the WE input and the data at ___ the rising edge of the WE input. The M37754FFCGP and the ___ M37754FFCHP start programming at the rising edge of the WE input in the second cycle and finishes programming within 10 ms as measured by its internal timer. Programming is performed in units of bytes. Note: A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer to Figure 12 for the programming flowchart. Program verify command The microcomputer enters the program verify mode by inputting command code "C016" in the first cycle. This command is used to verify the programmed data after executing the program command. The command code is latched into the internal command latch at the ___ rising edge of the WE input. When control signals are input in the second cycle at the timing shown in Figure 10, the M37754FFCGP and the M37754FFCHP output the programmed address's contents to the external. Since the address is internally latched when the program command is executed, there is no need to input it in the second cycle. VIH Address VIL tWC VIH CE VIL tCS tCH VIH OE VIL tRRW tWP VIH WE VIL tDS VIH Data VIL tVSC VPPH VPP VPPL 4016 tDH Program verify Program address tAS tAH Program tCS tCH tCS tCH tWPH tWP tDP tWP tWRR tDS tDS DIN tDH C016 tDH Dout Verify data output Fig. 10 Input/output timings during programming (Verify data is output at the same timing as for read.) 20 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Erase command The erase command is executed by inputting command code 2016 in the first cycle and command code 2016 again in the second cycle. The command code is latched into the internal command latch at the ___ rising edges of the WE input in the first cycle and in the second cycle, respectively. The erase operation is initiated at the rising edge of the ___ WE input in the second cycle, and the memory contents are collectively erased within 9.5 ms as measured by the internal timer. Note that data 0016 must be written to all memory locations before executing the erase command. Note: An erase operation is not completed by executing the erase command once. Always be sure to execute an erase verify command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 12 for the erase flowchart. Erase verify command The user must verify the contents of all addresses after completing the erase command. The microcomputer enters the erase verify mode by inputting the verify address and command code A016 in the first cycle. The address is internally latched at the falling edge of the ___ WE input, and the command code is internally latched at the rising ___ edge of the WE input. When control signals are input in the second cycle at the timing shown in Figure 11, the M37754FFCGP and the M37754FFCHP output the contents of the specified address to the external. Note: If any memory location where the contents have not been erased is found in the erase verify operation, execute the operation of "erase erase verify" over again. In this case, however, the user does not need to write data 0016 to memory locations before erasing. VIH Address VIL tWC VIH CE VIL tCS tCH VIH OE VIL tRRW tWP VIH WE VIL tDS VIH Data VIL tVSC VPPH VPP VPPL tDH tDH 2016 2016 tDS tWPH tWP tDE tCS tCH Erase Erase verify Verify address tAS tAH tCS tCH tWP tWRR tDS A016 Dout Verify data output tDH Fig. 11 Input/output timings during erasing (Verify data is output at the same timing as for read.) 21 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Reset command The reset command provides a means of stopping execution of the erase or program command safely. If the user inputs command code FF16 in the second cycle after inputting the erase or program command in the first cycle and again input command code FF16 in the third cycle, the erase or program command is disabled (i.e., reset), and the M37754FFCGP and the M37754FFCHP are placed in the read mode. If the reset command is executed, the contents of the memory does not change. Device identification code command By inputting command code 9016 in the first cycle, the user can read out the device identification code. The command code is latched into ___ the internal command latch at the rising edge of the WE input. At this time, the user can read out manufacture's code 1C16 (i.e., MITSUBISHI) by inputting 000016 to the address input pins in the second cycle; the user can read out device code D016 (i. e., 1M-bit flash memory) by inputting 000116. These command and data codes are input/output at the same timing as for read. 22 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Program START Erase START VCC = 5 V, VPP = VPPH VCC = 5 V, VPP = VPPH ADRS = first location YES ALL BYTES = 0016 ? NO X=0 WRITE PROGRAM COMMAND WRITE PROGRAM DATA DURATION = 10 s X=X+1 WRITE PROGRAM-VERIFY COMMAND DURATION = 6 s YES X = 25 ? NO FAIL PASS VERIFY BYTE ? PASS NO INC ADRS LAST ADRS ? NO YES WRITE READ COMMAND 0016 FAIL VERIFY BYTE ? FAIL 4016 PROGRAM ALL BYTES = 0016 ADRS = first location DIN X=0 WRITE ERASE COMMAND WRITE ERASE COMMAND DURATION = 9.5 ms X=X+1 WRITE ERASE-VERIFY COMMAND DURATION = 6 s 2016 C016 2016 A016 X = 1000 ? YES PASS VERIFY BYTE ? PASS VERIFY BYTE ? FAIL VPP = VPPL INC ADRS DEVICE PASSED DEVICE FAILED NO LAST ADRS ? YES WRITE READ COMMAND 0016 VPP = VPPL DEVICE PASSED DEVICE FAILED Fig. 12 Programming/Erasing algorithm flow chart 23 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, unless otherwise noted) Symbol ISB1 ISB2 ICC1 ICC2 ICC3 IPP1 IPP2 IPP3 VPPL VPPH VCC supply current (at standby) VCC supply current (at read) VCC supply current (at program) VCC supply current (at erase) VPP supply current (at read) VPP supply current (at program) VPP supply current (at erase) VPP supply voltage (read only) VPP supply voltage (read/write) Parameter Test conditions __ Min. Limits Typ. VCC = 5.5 V, CE = VIH VCC = 5.5 V, __ CE = VCC 0.2 V __ VCC = 5.5 V, CE = VIL, tRC = 150 ns, IOUT = 0 mA VPP = VPPH VPP = VPPH 0VPPVCC VCC Unit mA mA mA mA mA mA mA mA mA mA V V Note: VIH, VIL, VOH, VOL, IIH, and IIL for the control input, address input, and data input/output pins conform to the standards for microcomputer modes (e.g., memory expansion and microprocessor modes). AC ELECTRICAL CHARACTERISTICS Read-only mode Symbol tRC ta(AD) ta(CE) ta(OE) tCLZ tOLZ tDF tDH tWRR (Ta = 25 C, VCC = 5 V 10 %, unless otherwise noted) Parameter Read cycle time Address access time __ CE access time __ OE access time __ Output enable time (after CE) __ Output enable time (after OE) __ Output floating time (after OE) __ __ Output valid time (after CE, OE, address) Write recovery time (before read) Limits Min. 150 Max. 150 150 55 0 0 35 0 6 Unit ns ns ns ns ns ns ns ns ms Read/Write mode Symbol tWC tAS tAH tDS tDH tWRR tRRW tCS tCH tWP tWPH tDP tDE tVSC Write cycle time Address set up time Address hold time Data setup time Data hold time Write recovery time (before read) Read recovery time (before write) __ CE setup time __ CE hold time Write pulse width Write pulse waiting time Program time Erase time VPP setup time Parameter Limits Min. 150 0 60 50 10 6 0 20 0 60 20 10 9.5 1 Max. Unit ns ns ns ns ns ms ms ns ns ns ns ms ms ms Note : The read timing in the read/write mode is the same timing as in the read-only mode. 24 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Flash memory mode 2 (serial I/O mode) The M37754FFCGP and the M37754FFCHP have a function to serially input/output the software commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, and erase) using only a few pins. This is called the serial I/ O (input/output) mode. This mode can be selected by driving the __ SDA (serial data input/output), SCLK (serial clock input ), and OE pins high after connecting wires as shown in Figures 13, 14 and powering on the VCC pin and then applying VPPH to the VPP pin. In the serial I/O mode, the user can use seven types of software commands: bank (0, 1) select, read, program, program verify, auto erase, and error check. Serial input/output is accomplished synchronously with the clock, beginning from the LSB (LSB first). VCC P87 P86 P85 P84 P83 P82 P81 P80 VCC AVCC VREF AVSS VSS P77 P76 P75 P74 P73 P72 P71 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P27 P100 P101 P102 P103 P104 P105 P106 P107 P110 M37754FFCGP P111 P112 P113 P114 P115 P116 P117 P30 P31 P32 P33 VCC VSS E XOUT XIN RESET CNVSS BYTEVV P40 VSS V VPP Outline 100P6S-A BUSY SCLK SDA OE Fig. 13 Pin connection of M37754FFCGP when operating in serial I/O mode P70 P95 P94 P93 P92 P91 P90 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 V : Connect to the ceramic oscillation circuit. VV : Connect the BYTE pin to Vcc or Vss. indicates the flash memory pin. 25 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION VCC P02 P01 P00 P87 P86 P85 P84 P83 P82 P81 P80 VCC AVCC VREF AVSS VSS P77 P76 P75 P74 P73 P72 P71 P70 P95 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P27 P100 P101 P102 P103 P104 P105 P106 M37754FFCHP P107 P110 P111 P112 P113 P114 P115 P116 P117 P30 P31 P32 P33 VCC VSS E XOUT XIN RESET CNVSS BYTEUU P40 P41 P42 P43 VSS U VPP Outline 100P6Q-A V : Connect to the ceramic oscillation circuit. VV : Connect the BYTE pin to VCC or VSS. indicates the flash memory pin. Fig. 14 Pin connection of M37754FFCHP when operating in serial I/O mode 26 BUSY SCLK SDA OE P94 P93 P92 P91 P90 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Functional outline (Serial I/O mode) In the serial I/O mode, data is transferred synchronously with the clock using serial input/output. The input data is read from the SDA pin into the internal circuit synchronously with the rising edge of the serial clock pulse; the output data is output from the SDA pin synchronously with the falling edge of the serial clock pulse. Data is Table 4. Software command (Serial I/O mode) Number of transfers First command Command code input Bank 0 select E016 Bank 1 select E116 Read 0016 Program 4016 Program verify C016 Auto erase 3016 Error check 8016 Second ---------- ---------- Read address L (Input) Program address L (Input) Verify data (Output) 3016 (Input) Error code (Output) transferred in units of eight bits. In the first transfer, the user inputs the command code. This is followed by address input and data input/output according to the contents of the command. Table 4 shows the software commands used in the serial I/O mode. The following explains each software command. Third ---------- ---------- Read address H (Input) Program address H (Input) ---------- ---------- ---------- Fourth ---------- ---------- Read data (Output) Program data (Input) ---------- ---------- ---------- Bank select command This is the command which specifies the bank of the flash memory, which is to be read/programmed, before executing the read command or the program command (and the program verify command). There are the bank 0 select command (command code "E016"), which selects bank 0 (addresses 0000016 to 0FFFF16), and the bank 1 select command (command code "E116"), which selects bank 1 (addresses 1000016 to 1FFFF16). When any bank select command is input once, specified bank is valid until the next bank select command is input. Accordingly, when the read command or the program command (and the program verify command) is executed to plural bytes in the same bank, if any bank select command is input first, it is unnecessary to input the bank select command again for the following bytes. When selecting the serial I/O mode (before bank command input), bank 0 is selected. Note: Bank select command does not affect the auto erase command, that is to say, when executing the auto erase command, all flash memory is erased collectively regardless of specified bank. And in the same way, the bank select command does not affect the error check command. tCH SCLK SCLK tCH SDA 00000111 Command code input (E016) SDA 10000111 Command code input (E116) OE "H" OE "H" BUSY "L" BUSY "L" Bank 0 select command Bank 1 select command Fig. 15 Timings during bank select 27 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Read command Input command code 0016 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and pull the __ OE pin low. When this is done, the M37754FFCGP and the M37754FFCHP read out the contents of the specified address, and __ then latch it into the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the read data that has been latched into the data latch is serially output from the SDA pin. tCH SCLK A0 SDA A7 tCH A8 A15 D0 D7 00000000 Command code input (0016) Read address input (L) Read address input (H) tCR tWR tRC Read data output OE Read BUSY "L" Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit). Fig. 16 Timings during reading 28 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Program command Input command code 4016 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and then program data. Programming is initiated at the last rising edge of the serial clock during program data transfer. The BUSY pin is driven high during program operation. Programming is completed within 10 ms as measured by the built-in timer, and the BUSY pin is pulled low. Note : A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. In the case of failure in the verification, the user must repeatedly execute the program command until the pass in the verification. Refer to Figure 12 for the programming flowchart. tCH SCLK tCH tCH tPC A0 SDA 00000010 Command code input (4016) A7 A8 A15 D0 D7 Program address input (L) Program address input (H) Program data input OE tWP Program BUSY Fig. 17 Timings during programming Program verify command Input command code C016 in the first transfer. Proceed and drive the __ OE pin low. When this is done, the M37754FFCGP and the M37754FFCHP verify-read the programmed address's contents, __ and then latch it into the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the verify data that has been latched into the data latch is serially output from the SDA pin. SCLK D0 SDA 00000011 Command code input (C016) tCRPV OE Verify read BUSY "L" D7 Verify data output tWR tRC Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit). Fig. 18 Timings during program verify 29 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Auto erase command Input command code 3016 in the first transfer and command code 3016 again in the second transfer. When this is done, the M37754FFCGP and the M37754FFCHP execute an auto erase command. Auto erase is initiated at the last rising edge of the serial clock. The BUSY pin is driven high during the auto erase operation. Auto erase is completed when all memory contents are erased, and the BUSY pin is pulled low. Note: In the auto erase operation, the M37754FFCGP and the M37754FFCHP automatically repeat the erase and verify operations internally. Therefore, erase is completed by executing the command once. tCH SCLK tEC SDA 00001100 00001100 Command code input (3016) Command code input (3016) "H" OE Auto-erase BUSY Fig. 19 Timings at auto-erasing Error check command Input command code 8016 in the first transfer, and the M37754FFCGP and the M37754FFCHP output error information from the SDA pin, beginning at the next falling edge of the serial clock. If the E0 of the 8-bit error information is 1, it indicates that a command error has occurred. A command error means that some invalid commands other than commands shown in Table 4 has been input. When a command error occurs, the serial communication circuit sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. When being placed in this state, the serial communication circuit does not accept the subsequent serial clock and data (even including an error check command). Therefore, if the user wants to execute an error check command, temporarily drop the VPP pin input to the VPPL level to terminate the serial input/output mode. Then, place the M37754FFCGP and the M37754FFCHP into the serial I/O mode back again. The serial communication circuit is reset by this operation and is ready to accept commands. The error flag alone is not cleared by this operation, so the user can examine the serial communication circuit's error conditions before reset. This examination is done by the first execution of an error check command after the reset. The error flag is cleared when the user has executed the error check command. Because the error flag is undefined immediately after power-on, always be sure to execute the error check command. tCH SCLK E0 SDA 00000001 Command code input (8016) "H" ??????? Error flag output OE BUSY "L" Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit). Fig. 20 Timings at error checking 30 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION DC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, VPP = 12 V 5 %, unless otherwise noted) ICC, IPP-relevant standards during read, program, and erase are the same as in the parallel input/output mode. VIH, VIL, VOH, VOL, IIH, and IIL for __ the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes. AC ELECTRICAL CHARACTERISTICS (Ta = 25 C, VCC = 5 V 10 %, VPP = 12 V 5 %, f(XIN) = 40 MHz, unless otherwise noted) Symbol tCH tCR tWR tRC tCRPV tWP tPC tEC tc(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) td(C-Q) th(C-Q) th(C-E) tsu(D-C) th(C-D) Parameter Serial transmission interval Read waiting time after transmission Read pulse width Transfer waiting time after read Waiting time before program verify Programming time Transfer waiting time after programming Transfer waiting time after erase SCLK input cycle time SCLK high-level pulse width SCLK low-level pulse width SCLK rise time SCLK fall time SDA output delay time SDA output hold time SDA output hold time (only the 8th bit) SDA input set up time SDA input hold time Limits Min. Max. 400(Note 1) 400(Note 1) 320(Note 2) 400(Note 1) 6 10 400(Note 1) 400(Note 1) 250 100 100 20 20 0 90 0 120(Note 3) 200(Note 4) 30 90 Unit ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When f(XIN) = 25 MHz or less, calculate the minimum value according to formula 1. 1 x 10 x 109 f(XIN) 2: When f(XIN) = 25 MHz or less, calculate the minimum value according to formula 2. Formula 1 : 1x8 x 109 f(XIN) 3: When f(XIN) = 25 MHz or less, calculate the minimum value according to formula 3. Formula 2 : 1x3 x 109 f(XIN) 4: When f(XIN) = 25 MHz or less, calculate the minimum value according to formula 4 Formula 3 : Formula 4 : 1x5 f(XIN) x 109 AC waveforms tf(CK) tw(CKL) tc(CK) tr(CK) tw(CKH) SCLK th(C-Q) td(C-Q) th(C-E) Test conditions for AC characteristics SDA output * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V tsu(D-C) th(C-D) * Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC SDA input 31 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Flash memory mode-3 (CPU reprogramming mode) The M37754FFCGP and the M37754FFCHP have the CPU reprogramming mode where a built-in flash memory is handled by the central processing unit (CPU). 112 Kbytes (addresses 00100016 to 00EFFF16 and addresses 01100016 to 01EFFF16) of the 120-Kbyte flash memory shown in Figure 1 can be reprogrammed (erase and program). Remaining 8 Kbytes of the flash memory (addresses 00F00016 to 010FFF16) cannot be reprogrammed, but can be read. (It is possible to reprogram this remaining 8 Kbytes in the parallel I/O mode and the serial I/O mode). This area of 8 Kbytes can be used as an area where the control program of CPU reprogramming mode is stored. In CPU reprogramming mode, the flash memory is handled by writing and reading to/from the flash memory control register (see Figure 21) and the flash command register (see Figure 22). The CNVSS pin is used as the VPP power supply pin in CPU reprogramming mode. It is necessary to apply the power-supply voltage of VPPH from the external to this pin. Functional outline (Parallel input/output mode) Figure 21 shows the flash memory control register bit configuration. Figure 22 shows the flash command register bit configuration. Bit 0 of the flash memory control register is the CPU reprogramming mode select bit. When this bit is set to "1" and VPPH is applied to the CNVss/VPP pin, the CPU reprogramming mode is selected. Whether the CPU reprogramming mode is realized or not is judged by reading the CPU reprogramming mode monitor flag (bit 3 of the flash memory control register). Bit 1 is a busy flag which becomes "1" during auto erase, erase, and program execution. Whether these operations have been completed or not is judged by checking this flag after each command of auto erase, erase, and the program is executed. Bits 4, 5 of the flash memory control register are the erase/program area select bits. These bits specify an area where auto erase, erase, and program is operated. When the auto erase and the erase commands are executed after an area is specified by these bits, only the specified area is erased. Only for the specified area, programming is enabled; for the other areas, programming is disabled. Figure 23 shows the processor mode register 0 bit configuration in the CPU reprogramming mode. Set bit 1 to "0" (single-chip or memory expansion mode) in the CPU reprogramming mode. Set bit 2 (internal memory access bus cycle select bit) to "0." Be sure to set data length select flag m to "1" (8-bit length) beforehand because writing and reading of data are operated in unit of byte. 7 6 0 5 4 3 0 2 1 0 Flash memory control regsiter Address 6716 CPU reprogramming mode select bit (Notes 1, 2) 0 : CPU reprogramming mdoe is invalid. (Normal operation mode) 1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid. Auto erase/Erase/Program busy flag 0 : Auto erase, erase, and program are completed or not have been executed. 1 : Auto erase/erase/program is being executed. CPU reprogramming mode monitor flag 0 : CPU reprogramming mode is invalid. 1 : CPU reprogramming mode is valid. Fix this bit to "0." Erase/Program area select bits 0 ! : Addresses 00100016 to 00EFFF16 and addresses 01100016 to 01EFFF16 (total 112 Kbytes) 1 0 : Addresses 00100016 to 00EFFF16 (total 56 Kbytes) 1 1 : Addresses 01100016 to 01EFFF16 (total 56 Kbytes) Fix this bit to "0." Notes 1: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin. 2: When bit 0 is "1," the processor mode does not change even if VPPH is applied to the CNVSS/VPP pin. Fig. 21 Flash memory control register bit configuration 32 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION CPU reprogramming mode operation procedure The operation procedure in CPU reprogramming mode is described below. < Beginning procedure > Apply 0 V to the CNVss/VPP pin for reset release. Set the processor mode register 0 (see Figure 23). After CPU reprogramming mode control program is transferred to internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program). Set "1" (8-bit length) to data length select flag m. Set "1" to the CPU reprogramming mode select bit. Apply VPPH to the CNVSS/VPP pin. Read the CPU reprogramming mode monitor flag to confirm whether the CPU reprogramming mode is valid. The operation of the flash memory is executed by software-command-writing to the flash command register . Note: The following are necessary other than this: *Control for data which is input from the external (serial I/O etc.) and to be programmed to the flash memory *Initial setting for ports etc. *Writing to the watchdog timer < Release procedure > Apply 0V to the CNVSS/VPP pin. Set the CPU reprogramming mode select bit to "0." Each software command is explained as follows. Read command When "0016" is wr itten to the flash command register, the M37754FFCGP and the M37754FFCHP enter the read mode. The contents of the corresponding address can be read by reading the flash memory (For instance, with the LDA instruction etc.) under this condition. The read mode is maintained until another command code is written to the flash command register. Accordingly, after setting the read mode once, the contents of the flash memory can continuously be read. After reset and after the reset command is executed, the read mode is set. 7 6 0 5 4 3 2 0 1 0 0 Processor mode register 0 7 6 5 4 3 2 1 0 Flash command register Writing of software command Address 6516 Address 5E16 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 ! : Do not select. Internal memory access bus cycle select bit Fix this bit to "0." Software reset bit Interrupt priority detection time select bits Test mode bit Fix this bit to "0." Clock 1 output select bit Note: The flash command register is write-only register. Note: For the description of processor mode register 0, refer to Figure 14 on the M37754M8C-XXXGP data sheet. Fig. 22 Flash command register bit configuration Fig. 23 Processor mode register 0 bit configuration in CPU rewriting mode 33 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Program command When "4016" is written to the flash command register, the M37754FFCGP and the M37754FFCHP enter the program mode. Subsequently to this, if the instruction (for instance, STA or LDM instruction) for writing byte data in the address to be programmed is executed, the control circuit of the flash memory executes the program. The auto erase/erase/program busy flag of the flash memory control register is set to "1" when the program starts, and becomes "0" when the program is completed. Accordingly, after the write instruction is executed, CPU can recognize the completion of the program by polling this bit. The programmed area must be specified beforehand by the erase/ program area select bits. During programming, watchdog timer stops with "FFF16" set. Note: A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer to Figure 24 for the flow chart of the programming. Erase command When writing "2016" twice continuously to the flash command register, the flash memory control circuit performs erase to the area specified beforehand by the erase/program area select bits. Auto erase/erase/program busy flag of the flash memory control register becomes "1" when erase begins, and it becomes "0" when erase completes. Accordingly, CPU can recognize the completion of erase by polling this bit. Data "0016" must be written to all areas to be erased by the program and the program verify commands before the erase command is executed. During programming, watchdog timer stops with "FFF16" set. Note: The erasing operation is not completed by executing the erase command once. Always be sure to execute an erase verify command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 24 for the erasing flowchart. Erase verify command When "A016" is written to the flash command register, the M37754FFCGP and the M37754FFCHP enter the erase verify mode. Subsequently to this, if the instruction (for instance, LDA instruction) for reading byte data from the address to be verified, the contents of the address is read. CPU must erase and verify to all erased areas in a unit of address. If the address of which data is not "FF16" (i.e., data is not erased) is found, it is necessary to discontinue erasure verification there, and execute the operation of "erase erase verify" again. Note: By executing the operation of "erase erase verify" again when the memory not erased is found. It is unnecessary to write data "0016" before erasing in this case. Program verify command When "C016" is wr itten to the flash command register, the M37754FFCGP and the M37754FFCHP enter the program verify mode. Subsequently to this, if the instruction (for instance, LDA instruction) for reading byte data from the address to be verified (i.e., previously programmed address), the contents which has been written to the address actually is read. CPU compares this read data with data which has been written by the previous program command. In consequence of the comparison, if not agreeing, the operation of "program program verify" must be executed again. 34 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Program START Erase START ADRS = first location YES ALL BYTES = 0016 ? NO X=0 WRITE PROGRAM COMMAND WRITE PROGRAM DATA NOP ! 10 4016 PROGRAM ALL BYTES = 0016 ADRS = first location DIN X=0 WRITE ERASE COMMAND 2016 NO ERASE PROGRAM BUSY FLAG = 0 YES X=X+1 WRITE PROGRAM-VERIFY COMMAND DURATION = 6 s WRITE ERASE COMMAND NOP ! 10 C016 2016 NO ERASE PROGRAM BUSY FLAG = 0 YES X=X+1 X = 25 ? NO FAIL YES WRITE ERASE-VERIFY COMMAND PASS DURATION = 6 s A016 VERIFY BYTE ? PASS VERIFY BYTE ? FAIL X = 1000 ? INC ADRS NO LAST ADRS ? NO YES WRITE READ COMMAND 0016 PASS DEVICE PASSED DEVICE FAILED NO INC ADRS LAST ADRS ? YES WRITE READ COMMAND FAIL YES PASS VERIFY BYTE ? VERIFY BYTE ? FAIL 0016 DEVICE PASSED DEVICE FAILED Fig. 24 Flowchart when program/erase/auto erase is executed (1) 35 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Auto erase command When writing "3016" twice continuously to the flash command register, the flash memory control circuit executes the auto erase sequence described below for the area specified beforehand by the erase/program area select bits. (1) Data "0016" is written to the area to be erased in the flash memory. (2) The erasure is executed. (3) The contents of the erased flash memory is erase-verified one by one. When the address which is not erased is found, verification is interrupted, and after the erase command is executed again, erase-verification is operated again. (4) When the erasure of all areas specified to be erased, is confirmed by erase-verify-operation, the auto erase command is ended. The auto erase/erase/program busy flag of the flash memory control register becomes "1" when auto erase starts, and becomes "0" when auto erase completes. Accordingly, CPU can recognize the completion of auto erase by polling this bit. During auto erase, watchdog timer stops with "FF16" set. Note: When the flash memory is erased by using the auto erase command, it is unnecessary to execute the erase and erase verify commands. Figure 25 shows the flowchart when auto erase is executed. Reset command The reset command is a command to discontinue the program, erase, or the auto erase command on the way. When "FF16" is written to the command register two times continuously after "4016," "2016," or "3016" is written to the flash command register, the program, erase, or auto erase command becomes invalid (reset), and the M37754FFCGP and the M37754FFCHP enters the reset mode. The contents of the memory does not change even if the reset command is executed. Auto erase START WRITE AUTO-ERASE COMMAND WRITE AUTO-ERASE COMMAND 3016 3016 NOP ! 10 DC electric characteristics Note: The characteristic of the flash memory part are the same as the standard of the parallel I/O mode. NO ERASE PROGRAM BUSY FLAG = 0 YES AC electric characteristics Note: The characteristics are the same as the standards of the microcomputer mode. DEVICE PASSED Fig. 25 Flowchart when program/erase/auto erase is executed (2) 36 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION ABSOLUTE MAXIMUM RATINGS Symbol VCC AVCC VI VI Parameter Power source voltage Analog power source voltage Input voltage RESET, CNVSS, BYTE Input voltage P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, P100-P107, P110-P117, VREF, XIN Ratings -0.3 to 7 -0.3 to 7 -0.3 to 12 (Note) -0.3 to VCC+0.3 Unit V V V V Output voltage P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, P100-P107, P110-P117, XOUT, E Power dissipation Pd Operating temperature Topr Storage temerature Tstg Note: For the CNVss pin, this is 12.6 V when programming to the flash memory. VO -0.3 to VCC+0.3 300 -20 to 85 -40 to 150 V mW C C RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V10 %, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC AVCC VSS AVSS VIH VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOH(avg) IOH(avg) IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) Parameter Supply voltage Analog supply voltage Supply voltage Analog supply voltage High-level input voltage P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, XIN, ______ RESET, CNVSS, BYTE High-level input voltage P100-P107, P110-P117 (in single-chip mode) High-level input voltage P100-P107, P110-P117 (in memory expansion mode and microprocessor mode) Low-level input voltage P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, XIN, ______ RESET, CNVSS, BYTE Low-level input voltage P100-P107, P110-P117 (in single-chip mode) Low-level input voltage P100-P107, P110-P117 (in memory expansion mode and microprocessor mode) High-level peak output current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P92, P95, P100-P107, P110-P117 P93, P94 High-level average output current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P92, P95, P100-P107, P110-P117 P93, P94 Low-level peak output current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P54-P57, P60-P67, P70-P77, P80-P87, P90, P95, P100-P107, P110-P117 P50-P53, P91-P94 Low-level average output current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P54-P57, P60-P67, P70-P77, P80-P87, P90, P95, P100-P107, P110-P117 P50-P53,P91-P94 External clock frequency input (Note 3) Low-speed running High-speed running Limits Min. 4.5 Typ. 5.0 VCC 0 0 Max. 5.5 Unit V V V V V V V V V V mA mA mA mA mA mA mA mA MHz 0.8 VCC 0.8 VCC 0.5 VCC 0 0 0 VCC VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC -10 -20 -5 -15 10 20 5 15 25 40 Notes 1: Average output current is the averaage value of a 100 ms interval. 2: The sum of IOL(peak) for ports P0, P1, P2, P3, P8, P10, and P11 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, P8, P10, and P11 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, P7, and P9 must be 110 mA or less, the sum of IOH(peak) for ports P4, P5, P6, P7, and P9 must be 80 mA or less. 3: When the clock source select bit is "1," f(XIN)'s maximum limit is 12.5 MHz at low-speed running and is 20 MHz at high-speed running. 37 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz (Note)) Symbol Parameter Test conditions Min. Limits Typ. Max. Unit VOH VOH VOH VOH VOL VOL VOL VOL VT+--VT- High-level output voltage P00-P07, P10-P17, P20-P23, P27, P31, P33, P40-P47, P50-P57, P60-P67, P70-P77, IOH = -10 mA P80-P87, P90-P92, P95, P100-P107, P110-P117 High-level output voltage P00-P07, P10-P17, P20-P23, IOH = -400 A P27, P31, P33, P90-P92, P100-P107, P110-P117 _ High-level output voltage E, P30, P32 IOH = -10 mA IOH = -400 A IOH = -15 mA High-level output voltage P93, P94 IOH = -600 A Low-level output voltage P00-P07, P10-P17, P20-P23, P27, P31, P33, P40-P47, P54-P57, P60-P67,P70-P77, IOL = 10 mA P80-P87, P90, P95, P100-P107, P110-P117 Low-level output voltage P00-P07, P10-P17, P20-P23, P27, P31, P33, P90, IOL = 2 mA P100-P107, P110-P117 _ 3.4 V 4.8 3.4 4.8 3.4 4.8 V V V 2 V 0.45 1.6 0.4 2 0.4 0.4 0.2 0.1 1 V V V Low-level output voltage E, P30, P32 Low-level output voltage P50-P53, P91-P94 _____ ____ IOL = 10 mA IOL = 2 mA IOL = 20 mA IOL = 2 mA Hysteresis VT+--VT- VT+--VT- Hysteresis HOLD, RDY, TA0IN-TA4IN,_____ ____ ____ TB0IN-TB2IN, INT0-INT4, ADTRG, ____ ____ CTS0, CTS1, CLK0, CLK1, RxD0, RxD1 ______ _____ ____ RESET, HOLD, RDY V V V IIH IIL IIL VRAM Hysteresis XIN High-level input current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, P100-P107, P110-P117, XIN, RESET, CNVSS, BYTE Low-level input current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P53, P60-P67, P70-P77, P80-P87, P90-P95, P100-P107, P110-P117, XIN, RESET, CNVSS, BYTE Low-level input current P54-P57, P95 RAM hold voltage Power supply current (target value) 0.5 0.3 VI = 5 V 5 A VI = 0 V -5 A ICC VI = 0 V, No pull-up transistor -0.25 VI = 0 V, Pull-up transistor used 2 When clock is stoped. Output-only pin is f(XIN) = 40 MHz, square waveform (Note) open and other pins are Vss during Ta = 25 C when clcock is stopped. reset. Ta = 85 C when clcock is stopped. -0.5 -5 -1.0 50 1 A mA V mA 25 A 20 Note: f(XIN) = 20 MHz when the clock source select bit = "1." 38 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V 10 %, VSS = AVSS = 0 V, Ta = -20 to 85 C, the clock source select bit = 0, unless otherwise noted) Symbol ---------- Parameter Resolution VREF = VCC Test conditions A-D converter selected Comparator selected 10-bit mode 250 kHz AD 8-bit mode 12.5 MHz Comparator 250 kHz AD 8-bit mode 20 MHz (Note 1) Comparator 10-bit mode 8-bit mode Comparator 8-bit mode Comparator 10-bit mode 8-bit mode Comparator 5 5.9 4.9 1.4 2.45 0.7 4.72 3.92 1.12 2.7 0 Limits Typ. Unit Bits V LSB LSB mV LSB mV k Min. ---------- Absolute accuracy VREF = VCC RLADDER Ladder resistance VREF = VCC Max. 10 1 256 VREF 3 2 40 3 60 20 tCONV Conversion time AD = f(XIN)/4 High-speed selected running (f(XIN) 40 MHz) AD = f(XIN)/2 (Note 2) selected Low-speed running (f(XIN) 25 MHz) (Note 2) s VREF VIA Reference voltage Analog input voltage VCC VREF V V Notes 1: This is valid when the high-speed running is selected. 2: When the clock source select bit = 1, f(XIN) is 20 MHz or less at the high-speed running, and f(XIN) is 12.5 MHz or less at the low-speed running. D-A CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ---- ---- tsu RO IVREF Parameter Resolution Absolute accuracy Set time Output resistance Reference power supply input current Test conditions Limits Typ. Unit Bits % s k mA Min. 1 (Note) 2.5 Max. 8 1.0 3 4 3.2 Note: The test conditions are as follows: * One D-A converter is used. * The D-A register value of the unused D-A converter is "0016." * The reference power supply input current of the ladder resistance of the A-D converter is excluded. 39 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V10 %, VCC = 0 V, Ta = -20 to 85 C, unless otherwise noted) If the values depends on external clock frequency f(XIN), formulas of the limits are shown below. Also, the values at f(XIN) = 40 MHz in high speed running and at f(XIN) = 25 MHz in low-speed running are shown in ( ). At this time, the clock source select bit is "0." When the clock source select bit is "1", regard f(XIN) in tables as 2*f(XIN). The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 40 40 Max. Unit ns ns ns Timer A input (Gating input in timer mode) Symbol Parameter f(XIN) 40 MHz tc(TA) TAiIN input cycle time (XIN) 25 MHz f(XIN) 40 MHz tw(TAH) TAiIN input high-level pulse width f(XIN) 25 MHz f(XIN) 40 MHz tw(TAL) TAiIN input low-level pulse width f(XIN) 25 MHz Limits Min. 16 x 109 (400) f(XIN) 8 x 109 (320) f(XIN) 8 x 109 (200) f(XIN) 9 4 x 10 (160) f(XIN) 9 8 x 10 (200) f(XIN) 4 x 109 f(XIN) (160) Max. Unit ns ns ns ns ns ns Note : The TAiIN input cycle time requires 4 or more cycles of count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running (f(XIN) 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) 25 MHz). At this time, the clock source select bit is "0." Timer A input (External trigger input in one-shot pulse mode) Symbol Parameter f(XIN) 40 MHz tc(TA) TAiIN input cycle time f(XIN) 25 MHz Limits Min. 8 x 109 (200) f(XIN) 9 4 x 10 (160) f(XIN) 80 80 Max. Unit ns ns ns ns tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 80 Max. Unit ns ns Timer A input (Up-down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns 40 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timer A input (Two-phase pulse input in event counter mode) Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAiIN input cycle time TAjIN input setup time TAjOUT input setup time Parameter Limits Min. 800 200 200 Max. Unit ns ns ns * Count input in event counter mode * Gating input in timer mode * External trigger input in one-shot pulse mode * External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) * Up-down and count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input) tw(UPL) TAiOUT input (Up-down input) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count by falling) TAiIN input (When count by rising) * Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjOUT input tsu(TAjOUT-TAjIN) Test conditions * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V 41 PR e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som I LIM E Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol Parameter f(XIN) 40 MHz tc(TB) TBiIN input cycle time f(XIN) 25 MHz f(XIN) 40 MHz tw(TBH) TBiIN input high-level pulse width f(XIN) 25 MHz f(XIN) 40 MHz tw(TBL) TBiIN input low-level pulse width f(XIN) 25 MHz Limits Min. 16 x 109 (400) f(XIN) 8 x 109 (320) f(XIN) 9 8 x 10 (200) f(XIN) 9 4 x 10 (160) f(XIN) 9 8 x 10 (200) f(XIN) 4 x 109 (160) f(XIN) Max. Unit ns ns ns ns ns ns Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running (f(XIN) 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) 25 MHz). At this time, the clock source select bit is "0." Timer B input (Pulse width measurement mode) Symbol Parameter f(XIN) 40 MHz tc(TB) TBiIN input cycle time f(XIN) 25 MHz f(XIN) 40 MHz tw(TBH) TBiIN input high-level pulse width f(XIN) 25 MHz f(XIN) 40 MHz tw(TBL) TBiIN input low-level pulse width f(XIN) 25 MHz Limits Min. 16 x 109 (400) f(XIN) 9 8 x 10 (320) f(XIN) 9 8 x 10 (200) f(XIN) 4 x 109 (160) f(XIN) 9 8 x 10 (200) f(XIN) 9 4 x 10 (160) f(XIN) Max. Unit ns ns ns ns ns ns Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running (f(XIN) 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) 25 MHz). At this time, the clock source select bit is "0." A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (minimum allowable trigger) ADTRG input low-level pulse width Limits Min. 1000 125 Max. Unit ns ns 42 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Parameter Limits Min. 200 100 100 0 20 90 Max. Unit ns ns ns ns ns ns ns 80 External interrupt INTi input Symbol tw(INH) tw(INL) INTi input high-level pulse width INTi input low-level pulse width Parameter Limits Min. 250 250 Max. Unit ns ns tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C - Q) TxDi td(C - Q) RxDi tw(INL) tsu(D - C) th(C - D) INTi input Test conditions * Vcc = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V,VOH = 2.0 V,CL = 100 pF tw(INH) 43 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION READY, HOLD TIMING Timing requirements (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0", unless otherwise noted) The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Symbol Parameter RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Limits Min. 42 42 0 0 Max. Unit ns ns ns ns tsu(RDY-1) tsu(HOLD-1) th(1-RDY) th(1-HOLD) : f(XIN) = 20 MHz when the clock source select bit = "1". Switching characteristics Symbol td(1-HLDA) tpxz(HLDA-RDZ) tpxz(HLDA-WRZ) tpxz(HLDA-BHEZ) tpxz(HLDA-AZ) tpxz(HLDA-DLZ/DHZ) tpzx(HLDA-RDZ) tpzx(HLDA-WRZ) tpzx(HLDA-BHEZ) tpzx(HLDA-AZ) tpzx(HLDA-DLZ/DHZ) (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0", unless otherwise noted) Parameter Limits Min. Max. 50 50 50 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns : f(XIN) = 20 MHz when the clock source select bit = "1". HLDA output delay time Floating start delay time (at hold state) Floating start delay time (at hold state) Floating start delay time (at hold state) Floating start delay time (at hold state) Floating start delay time (at hold state) Floating release delay time (at hold state) Floating release delay time (at hold state) Floating release delay time (at hold state) Floating release delay time (at hold state) Floating release delay time (at hold state) 0 0 0 0 0 44 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION RDY input 1 (when 3- access in high-speed running) RD,WR RDY input tsu(RDY-1) th(1-RDY) V RDY input is always sampled at the falling edge of 1 just before the RD and WR signals' rise regardless of the bus mode and the number of waits. HOLD input 1 tsu(HOLD-1) th(1-HOLD) HOLD input td(1-HLDA) td(1-HLDA) HLDA output tpxz(HLDA-RDZ) Hi-Z RD tpzx(HLDA-WRZ) Hi-Z WR tpzx(HLDA-RDZ) tpxz(HLDA-WRZ) tpxz(HLDA-BHE) Hi-Z BHE output tpzx(HLDA-BHE) tpxz(HLDA-AZ) A0-A7 output A8-A15 output A16-A23 output tpxz(HLDA-DLZ/DHZ) D0-D7 output D8-D15 output (BYTE ="L") Hi-Z Hi-Z tpzx(HLDA-AZ) tpzx(HLDA-DLZ/DHZ) Test conditions * VCC = 5 V10 % * RDY input, HOLD input : VIL = 1.0 V, VIH = 4.0 V * HLDA output : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 45 PRE e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som I LIM Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timing requirements (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0" V, unless otherwise noted) V The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Single-chip mode Symbol tc tw(H) tw(L) tr tf tsu(PiD-E) th(E-PiD) Parameter External clock input cycle time (Note 1) External clock input high-level pulse width (Note 2) External clock input low-level pulse width (Note 2) External clock rise time External clock fall time Port Pi input setup time (i = 0--11) Port Pi input hold time (i = 0--11) Limits Min. Max. 25 tc/2 - 8 tc/2 - 8 8 8 60 0 Unit ns ns ns ns ns ns ns V: f(XIN) = 20 MHz when the clock source select bit = "1" Notes 1: When the clock source select bit = "1", tc's minimum limit is 50 ns. 2: When the clock source select bit = "1", set tw(H)/tc and tw(L)/tc ratios to 45 to 55 %. Switching characteristics (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0" V, unless otherwise noted) (Single-chip mode) Symbol td(E-PiQ) Parameter Port Pi data output delay time (i = 0--11) Limits Min. Max. 60 Unit ns V: f(XIN) = 20 MHz when the clock source select bit = "1" tr f(XIN) tf tc tw(H) tw(L) E td(E - PiQ) Port Pi output (i = 0--11) tsu(PiD - E) Port Pi input (i = 0--11) Test conditions * VCC = 5 V10 % * Intput timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF th(E - PiD) 46 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timing requirements (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz when the clock source select bit = "0", unless otherwise noted) V The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Memory expansion and Microprocessor mode : Low-speed running Symbol tc tw(H) tw(L) tr tf tsu(DH-RD) tsu(DL-RD) tsu(PiD-RD) th(RD-DH) th(RD-DL) th(RD-PiD) tsu(A-DL/DH) Parameter External clock input cycle time (Note 1) External clock input high-level pulse width (Note 2) External clock input low-level pulse width (Note 2) External clock rise time External clock fall time High-order data input setup time (BYTE = "L") Low-order data input setup time Port Pi input setup time (i = 4--9, 11) High-order data input hold time (BYTE = "L") Low-order data input hold time Port Pi input hold time (i = 4--9, 11) Data setup time with address stabilized (Note 3) Limits Unit Min. Max. 40 ns tc/2 - 8 ns tc/2 - 8 ns 8 ns 8 ns 30 ns 30 ns 60 ns 0 ns 0 ns 0 ns 60 (2- access) 140 (3- access) ns 220 (4- access) 60 (2- access) 140 (3- access) ns 220 (4- access) 55 (2- access) 135 (3- access) ns 215 (4- access) tsu(CS-DL/DH) Data setup time with chip select stabilized (Note 3) tsu(LA-DL) Data setup time with address stabilized (Note 3) : f(XIN) = 12.5 MHz when the clock source selet bit = "1" Notes 1: When the clock source select bit = "1", tc's minimum limit is 80 ns. 2: When the clock source select bit = "1", set tw(H)/tc and tw(L)/tc ratios to 45 to 55 %. 3: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the page after the next page. 47 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Switching characteristics (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz when the clock source select bit = "0", unless otherwise noted) Memory expansion and Microprocessor mode : Low-speed running Symbol tw(H), tw(L) td(1-WR) td(1-RD) __ tw(WR) __ tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) td(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) td(ALE-WR) td(ALE-RD) tw(ALE) th(WR-A) th(RD-A) th(WR-BHE) th(RD-BHE) th(WR-CS) th(RD-CS) th(WR-DLQ/DHQ) tpzx(WR-DLZ/DHZ) td(LA-WR) td(LA-RD) td(LA-ALE) th(ALE-LA) tpxz(RD-DLZ) tpzx(RD-DLZ) td(WR-PiQ) Parameter 2- access Min. Max. 20 -7 12 -7 12 60 60 15 15 8 15 15 8 15 15 8 35 30 4 4 22 10 10 10 10 10 10 15 0 12 12 5 9 5 18 60 3- access 4- access Min. Max. Min. Max. 20 20 -7 12 -7 12 -7 12 -7 12 140 140 140 140 15 95 15 95 8 55 15 95 15 95 8 55 15 95 15 95 8 55 35 35 30 30 4 4 4 4 22 62 10 10 10 10 10 10 10 10 10 10 10 10 15 15 0 0 12 92 12 92 5 52 9 25 (Note) 5 5 18 18 60 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns high-level pulse width, low-level pulse width (Note) ___ WR output delay time __ RD output delay time ___ WR low-level pulse width (Note) RD low-level pulse width (Note) Address output delay time (Note) Address output delay time (Note) Address output delay time (Note) ____ BHE output delay time (Note) ____ BHE output delay time (Note) ____ BHE output delay time (Note) Chip select output delay time (Note) Chip select output delay time (Note) Chip select output delay time (Note) Data output delay time Floating start delay time (Note) ALE output delay time ALE output delay time ALE pulse width (Note) Address hold time (Note) Address hold time (Note) BHE hold time (Note) BHE hold time (Note) Chip select hold time (Note) Chip select hold time (Note) Data hold time (Note) Floating release delay time Address output delay time (Note) Address output delay time (Note) Address output delay time (Note) Address hold time Floating start delay time Floating release delay time (Note) Port Pi data output delay time (i = 4--9, 11) : f(XIN) = 12.5 MHz when the clock source selet bit = "1" Note: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the next page. 48 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Bus timing data formulas Memory expansion and Microprocessor mode : Low-speed running (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) 25 MHz when the clock source select bit = "0", unless otherwise noted) Symbol tsu(A-DL/DH) tsu(CS-DL/DH) tw(H), tw(L) tw(WR), tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) tw(ALE) th(WR-A) th(RD-A) td(WR-BHE) td(RD-BHE) td(WR-CS) td(RD-CS) th(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) tsu(LA-DL) td(LA-WR) td(LA-RD) td(LA-ALE) th(ALE-LA) tpzx(RD-DLZ) __ __ Parameter Data setup time with address stabilized Data setup time with chip select stabilized 2- access 3 x 109 f(XIN) 3 x 109 f(XIN) 1 x 109 f(XIN) 2 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 3 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) - 60 - 60 - 20 - 20 - 25 - 25 - 32 - 25 - 25 - 32 - 25 - 25 - 32 - 18 - 30 - 30 - 30 - 30 - 30 - 30 - 25 - 10 - 65 - 28 - 28 - 35 3- access 5 x 109 f(XIN) - 60 5 x 109 f(XIN) - 60 4- access 7 x 109 f(XIN) - 60 7 x 109 f(XIN) - 60 Unit ns ns ns high-level pulse width, f low-level pulse width ___ ___ WR, RD low-level pulse width Address output delay time Address output delay time Address output delay time ____ 4x f(XIN) - 20 109 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 2 x 109 f(XIN) - 25 - 25 - 65 - 25 - 25 - 65 - 25 - 25 - 65 - 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns BHE output delay time ____ BHE outupt delay time ____ BHE output delay time Chip select output delay time Chip select output delay time Chip select output delay time ALE pulse width Address hold time Address hold time ____ BHE hold time ____ BHE hold time Chip select hold time Chip select holt time Data hold time Floating start delay time Data setup time with address stabilized Address output delay time Address output delay time Address output delay time Address hold time Floating release delay time 5x - 65 f(XIN) 109 7x f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 2 x 109 f(XIN) 1 x 109 f(XIN) 109 - 65 - 28 - 28 - 28 - 15 ns ns ns ns ns ns V: f(XIN) 12.5 MHz when the clock source select bit = "1" Note: When the clock source select bit is "1", regard f(XIN) in tables as 2*f(XIN). 1x f(XIN) - 22 109 49 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 2- access in low-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) tr tf tc td(1-WR) td(1-WR) RD WR tw(WR) tw(ALE) ALE output td(ALE-WR) td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0 to A7 output A8 toA15 output A16 toA23 output td(A-ALE) td(CS-WR) CS0 to CS4 output td(CS-ALE) td(WR-DLQ/DHQ) Chip select Address th(WR-BHE) th(WR-A) th(WR-CS) th(WR-DLQ/DHQ) D0 to D7 output D8 to D15 output (BYTE = "L") Hi-Z Output data tpxz(WR-DLZ/DHZ) tpzx(WR-DLZ/DHZ) td(LA-WR) D0/LA0 to D7/LA7 output (multiplex bus (Note)) Address th(ALE-LA) td(LA-ALE) td(WR-PiQ) Port Pi output td(WR-DLQ) Data th(WR-DLQ) Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (Port Pi, f(XIN)) Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Data input : VIL = 0.8 V, VIH = 2.5 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 50 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 2- access in low-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-RD) td(1-RD) tr tf tc RD tw(RD) WR tw(ALE) ALE output td(ALE-RD) td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE = "L") Hi-Z tsu(DL/DH-RD) Input data Chip select Address th(RD-BHE) th(RD-A) th(RD-CS) th(RD-DL/DH) td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) td(LA-ALE) D0--D7 input (multiplex bus (Note)) Address tpxz(RD-DLZ) tpzx(RD-DLZ) th(ALE-LA) tsu(LA-DL) tsu(DL-RD) th(RD-DL) Data tsu(PiD-RD) Port Pi input Input data th(RD-PiD) Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V 51 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 3- access in low-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-WR) td(1-WR) tr tf tc RD WR tw(WR) tw(ALE) ALE output td(ALE-WR) td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output td(CS-ALE) Chip select Address th(WR-BHE) th(WR-A) th(WR-CS) td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") td(LA-WR) D0/LA0--D7/LA7 output (multiplex bus (Note)) td(LA-ALE) Address th(ALE-LA) Output data tpzx(WR-DLZ/DHZ) td(WR-DLQ) Data th(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) th(WR-DLQ) td(WR-PiQ) Port Pi output Note: These become a multiplex bus only when all of the following conditions are satisfied: *BYTE = "H" *Multiplex bus select bit = "1" *While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 52 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 3- access in low-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-RD) td(1-RD) tr tf tc RD tw(RD) WR tw(ALE) ALE output td(ALE-RD) td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output Address td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(CS-DL/DH) tsu(A-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE = "L") td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) D0--D7 input (multiplex bus (Note)) Address td(LA-ALE) th(ALE-LA) tsu(DL-RD) tsu(LA-DL) Data tpxz(RD-DLZ) tsu(DL/DH-RD) Input data Chip select th(RD-BHE) th(RD-A) th(RD-CS) th(RD-DL/DH) tpzx(RD-DLZ) th(RD-DL) tsu(PiD-RD) Port Pi input Input data th(RD-PiD) Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 53 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 4- access in low-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-WR) td(1-WR) tr tf tc RD WR tw(WR) tw(ALE) ALE output td(ALE-WR) td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0-A7 output A8-A15 output A16-A23 output td(A-ALE) td(CS-WR) CS0-CS4 output td(CS-ALE) Chip select Address th(WR-BHE) th(WR-A) th(WR-CS) td(WR-DLQ/DHQ) D0-D7 output D8-D15 output (BYTE = "L") tpzx(WR-DLZ/DHZ) Output data th(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) td(LA-WR) D0/LA0-D7/LA7 output (multiplex bus (Note)) Address td(LA-ALE) td(WR-DLQ) Data th(ALE-LA) th(WR-DLQ) td(RD-PiQ) Port Pi output Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 54 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 4- access in low-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-RD) td(1-RD) tr tf tc RD tw(RD) WR tw(ALE) ALE output td(ALE-RD) td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) Chip select Address th(RD-BHE) th(RD-A) th(RD-CS) tsu(CS-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE ="L") td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) Address td(LA-ALE) D0--D7 input (multiplex bus (Note)) th(ALE-LA) tsu(LA-DL) tsu(DL-RD) th(RD-DL) Data tpxz(RD-DLZ) tpzx(RD-DLZ) tsu(DL/DH-RD) Input data th(RD-DL/DH) tsu(PiD-RD) Port Pi input Input data th(RD-PiD) Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 55 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Timing requirements (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN)=40 MHz when the clock source select bit = "0", unless otherwise noted) V The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Memory expansion and Microprocessor mode : High-speed running Symbol tc tw(H) tw(L) tr tf tsu(DH-RD) tsu(DL-RD) tsu(PiD-RD) th(RD-DH) th(RD-DL) th(RD-PiD) tsu(A-DL/DH) Parameter External clock input cycle time (Note 1) External clock input high-level pulse width (Note 2) External clock input low-level pulse width (Note 2) External clock rise time External clock fall time High-order data input setup time (BYTE = "L") Low-order data input setup time Port Pi input setup time (i = 4--9, 11) High-order data input hold time (BYTE = "L") Low-order data input hold time Port Pi input hold time (i = 4--9, 11) Data setup time with address stabilized (Note 3) Limits Min. 25 tc/2 - 8 tc/2 - 8 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns 8 8 30 30 60 0 0 0 65 (3- access) 110 (4- access) 160 (5- access) 65 (3- access) 110 (4- access) 160 (5- access) 50 (3- access) 100 (4- access) 150 (5- access) tsu(CS-DL/DH) Data setup time with chip select stabilized (Note 3) ns tsu(LA-DL) Data setup time with address stabilized (Note 3) ns : f(XIN) = 20 MHz when the clock source selet bit = "1" Notes 1: When the clock source select bit = "1", tc's minimum limit is 50 ns. 2: When the clock source select bit = "1", set tw(H)/tc and tw(L)/tc ratios to 45 to 55 %. 3: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the page after the next page. 56 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Switching characteristics (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0", unless otherwise noted) Memory expansion and Microprocessor mode : High-speed running Symbol tw(H), tw(L) td(1-WR) td(1-RD) __ tw(WR) __ tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) td(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) td(ALE-WR) td(ALE-RD) tw(ALE) th(WR-A) th(RD-A) th(WR-BHE) th(RD-BHE) th(WR-CS) th(RD-CS) th(WR-DLQ/DHQ) tpzx(WR-DLZ/DHZ) td(LA-WR) td(LA-RD) td(LA-ALE) th(ALE-LA) tPXZ(RD-DLZ) tPZX(RD-DLZ) td(WR-PiQ) Parameter 3- access Min. Max. 5 -7 12 -7 12 55 55 25 25 10 25 25 10 25 25 10 35 30 4 4 10 10 10 10 10 10 10 15 0 15 15 5 10 5 15 60 4- access Min. Max. 5 -7 12 -7 12 80 80 45 45 35 45 45 35 45 45 35 35 30 4 4 35 10 10 10 10 10 10 15 0 40 40 30 10 5 15 60 5- access Min. Max. 5 -7 12 -7 12 130 130 45 45 35 45 45 35 45 45 35 35 30 4 4 35 10 10 10 10 10 10 15 0 40 40 30 10 5 15 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns : f(XIN) = 20 MHz when the clock source selet bit = high-level pulse width, low-level pulse width ___ WR output delay time ___ RD output delay time ___ WR low-level pulse width ___ RD low-level pulse width Address output delay time Address output delay time Address output delay time ____ BHE output delay time ____ BHE output delay time ____ BHE output delay time Chip select output delay time Chip select output delay time Chip select output delay time Data output delay time Floating start delay time ALE output delay time ALE output delay time ALE pulse width Address hold time Address hold time ____ BHE hold time ____ BHE hold time Chip select hold time Chip select hold time Data hold time Floating release delay time Address output delay time Address output delay time Address output delay time Address hold time Floating start delay time Floating release delay time Port Pi data output delay time (i = 4--9, 11) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) "1" Note: Since the values depend on external clock frequency f(XIN), calculate them by using the bus timing data formulas on the next page. 57 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION Bus timing data formulas Memory expansion and Microprocessor mode : High-speed running (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) 40 MHz when the clock source select bit = "0", unless otherwise noted) Symbol tsu(A-DL/DH) tsu(CS-DL/DH) tw(H), tw(L) tw(WR), tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) tw(ALE) th(WR-A) th(RD-A) td(WR-BHE) td(RD-BHE) td(WR-CS) td(RD-CS) th(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) tsu(LA-DL) td(LA-WR) td(LA-RD) td(LA-ALE) td(ALE-LA) tpzx(RD-DLZ) __ __ Parameter Data setup time with address stabilized Data setup time with chip select stabilized 3- access 5 x 109 f(XIN) 5 x 109 f(XIN) 1 x 109 f(XIN) 3 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 1 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 1 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 5 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) - 60 - 60 - 20 - 20 - 25 - 25 - 15 - 25 - 25 - 15 - 25 - 25 - 15 - 15 - 15 - 15 - 15 - 15 - 15 - 15 - 10 +5 4- access 7 x 109 f(XIN) - 65 7 x 109 f(XIN) - 65 5- access 9 x 109 f(XIN) - 65 9 x 109 f(XIN) - 65 Unit ns ns ns high-level pulse width, low-level pulse width ___ ___ WR, RD low-level pulse width Address output delay time Address output delay time Address output delay time ____ BHE outuput delay time ____ BHE outuput delay time ____ BHE outuput delay time Chip select output delay time Chip select output delay time Chip select output delay time ALE pulse width Address hold time Address hold time ____ 4x f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 2 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 2 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 109 - 20 - 30 - 30 - 15 - 30 - 30 - 15 - 30 - 30 - 15 - 15 6x f(XIN) 109 - 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns BHE hold time ____ BHE hold time Chip select hold time Chip select hold time Data hold time Floating start delay time Data setup time with address stabilized Address outuput delay time Address outuput delay time Address outuput delay time Address hold time Floating release delay time 7x f(XIN) 3 x 109 - 35 f(XIN) 3 x 109 - 35 f(XIN) 2 x 109 - 20 f(XIN) - 75 109 - 15 - 10 - 75 - 35 - 35 - 20 9 - 75 f(XIN) x 10 9 ns ns ns ns ns ns V: f(XIN) 20 MHz when the clock source select bit = "1" Note: When the clock source select bit is "1", regard f(XIN) in tables as 2*f(XIN). 58 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 3- access in high-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) tr tf tc td(1-WR) td(1-WR) RD WR tw(WR) tw(ALE) ALE output td(ALE-WR) td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output Chip select Address th(WR-BHE) th(WR-A) th(WR-CS) td(CS-ALE) td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") Output data tpzx(WR-DLZ/DHZ) tpxz(WR-DLZ/DHZ) th(WR-DLQ/DHQ) td(LA-WR) D0/LA0--D7/LA7 output (multiplex bus (Note)) td(LA-ALE) Address td(WR-DLQ) th(WR-DLQ) Data th(ALE-LA) td(WR-PjQ) Port Pi output Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 59 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 3- access in high-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) tr tf tc td(1-RD) td(1-RD) RD tw(RD) WR tw(ALE) ALE output td(ALE-RD) td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE = "L") tpxz (RD-DLZ) td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) D0--D7 input (multiplex bus (Note)) tsu(DL/DH-RD) Input data Chip select Address th(RD-BHE) th(RD-A) th(RD-CS) th(RD-DL/DH) tpzx(RD-DLZ) Address td(LA-ALE) th(ALE-LA) tsu (LA-DL) Data tsu(DL-RD) th(RD-DL) tsu(PiD-RD) Port Pi input Input data th(RD-PiD) Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 60 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 4- access in high-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-WR) td(1-WR) tr tf tc RD WR tw(WR) tw(ALE) ALE output td(ALE-WR) td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output td(CS-ALE) Chip select Address th(WR-BHE) th(WR-A) th(WR-CS) td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") tpzx(WR-DLZ/DHZ) td(WR-DLQ) td(LA-WR) D0/LA0--D7/LA7 output (multiplex bus (Note)) Address td(LA-ALE) th(ALE-LA) Data Output data th(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) th(WR-DLQ) td(WR-PiQ) Port Pi output Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 61 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 4- access in high-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw (H) tr tf tc td(1-RD) td(1-RD) RD tw(RD) WR tw(ALE) ALE output td(ALE-RD) td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output Address td(A-ALE) td(CS-RD) CS0-CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(A-DL/DH) D0-D7 input D8-D15 input (BYTE = "L") tpxz(RD-DLZ) td(LA-RD) LA0-LA7 output (D0/LA0-D7/LA7) (multiplex bus (Note)) Address td(LA-ALE) D0-D7 input (multiplex bus (Note)) th(ALE-LA) tsu(LA-DL) Data tsu(DL-RD) tsu(DL/DH-RD) Input data Chip select th(RD-BHE) th(RD-A) th(RD-CS) th(RD-DL/DH) tpzx(RD-DLZ) th(RD-DL) tsu(PiD-RD) Port Pi input Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Input data th(RD-PiD) Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 62 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 5- access in high-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-WR) td(1-WR) tr tf tc RD WR tw(WR) tw(ALE) ALE output td(ALE-WR) td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output td(CS-ALE) Chip select Address th(WR-BHE) th(WR-A) th(WR-CS) th(WR-DLQ/DHQ) td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") tpzx(WR-DLZ/DHZ) tpxz(WR-DLZ/DHZ) td(WR-DLQ) td(LA-WR) D0/LA0--D7/LA7 output (multiplex bus (Note)) Address td(LA-ALE) th(ALE-LA) Data th(WR-DLQ) Output data td(WR-PiQ) Port Pi output Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 63 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (when 5- access in high-speed running tw(H) tw(L) f(XIN) tw(L) 1 tw(H) tr tf tc td(1-RD) td(1-RD) RD tw(RD) WR tw(ALE) ALE output td(ALE-RD) td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE = "L") tpxz(RD-DLZ) td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) D0--D7 input (multiplex bus (Note)) Address td(LA-ALE) th(ALE-LA) tsu(LA-DL) Chip select Address th(RD-BHE) th(RD-A) th(RD-CS) tsu(DL/DH-RD) Input data th(RD-DL/DH) tpzx(RD-DLZ) tsu(DL-RD) th(RD-DL) Data tsu(PiD-RD) Port Pi input Input data th(RD-PiD) Note: These become a multiplex bus only when all of the following conditions are satisfied: *BYTE = "H" *Multiplex bus select bit = "1" *While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 64 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR ITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) 40 MHz when the clock source select bit = "0") f (XIN) = 40 MHz Symbol Parameter Min. Max. tw(H), tw(L) td(1-WR) td(1-RD) tw(WR) tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) td(WR-DLQ/DHQ) __ __ Bus timing data formula 1 x 109 f(XIN) - 20 Unit ns ns ns high-level pulse width, low-level pulse width ___ 5 -7 -7 5 5 25 25 10 25 25 10 25 25 10 35 30 4 4 10 10 10 10 10 10 10 15 0 12 12 WR output delay time ___ RD output delay time ___ WR low-level pulse width ___ RD low-level pulse width Address output delay time Address output delay time Address output delay time ____ BHE output delay time ____ BHE output delay time ____ BHE output delay time Chip select output delay time Chip select output delay time Chip select output delay time Data output delay time 1x f(XIN) 1 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 109 - 20 - 20 - 25 - 25 - 40 - 25 - 25 - 40 - 25 - 25 - 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -------- 1x f(XIN) + 5 109 -------- -------- 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) - 15 - 15 - 15 - 15 - 15 - 15 - 15 - 10 tpxz(WR-DLZ/DHZ) Floating start delay time td(ALE-WR) td(ALE-RD) tw(ALE) th(WR-A) th(RD-A) td(WR-BHE) td(RD-BHE) td(WR-CS) td(RD-CS) th(WR-DLQ/DHQ) ALE output delay time ALE output delay time ALE pulse width Address hold time Address hold time ____ BHE hold time ____ BHE hold time Chip select hold time Chip select hold time Data hold time tpzx(WR-DLZ/DHZ) Floating release delay time -------- : f(XIN) 20 MHz when the clock source select bit = "1". : f(XIN) = 20 MHz when the clock source select bit = "1". 65 PR . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37754FFCGP M37754FFCHP SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION (External bus timing on internal RAM access (2- access) in high-speed running) tw(H) tw(L) f(XIN) tw(L) 1 tw(H) tr tf tc tw(H) tw(L) tr tf tc tw(L) td(1-WR) td(1-WR) tw(H) td(1-RD) td(1-RD) RD tw(RD) WR tw(WR) tw(ALE) td(ALE-WR) ALE output tw(ALE) td(ALE-RD) td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output td(CS-ALE) Address th(WR-BHE) td(BHE-RD) th(RD-BHE) th(WR-A) td(BHE-ALE) td(A-RD) Address td(A-ALE) th(RD-A) th(WR-CS) td(CS-RD) td(CS-ALE) th(RD-CS) td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") Hi-Z tpzx(WR-DLZ/DHZ) Data th(WR-DLQ/DHQ) Hi-Z tpxz(WR-DLZ/DHZ) V The value of output data is undefined. Test conditions * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF 66 Keep safety first in your circuit designs! * Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials * * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. * * * * (c) 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Apr. 1999. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 First Edition M37754FFCGP, M37754FFCHP DATA SHEET Revision Description Rev. date 971114 990428 2.00 (1) For the "timer A write flag (address 4516)", it's name is corrected: * New register name: timer A write register * Related pages: pages 11, 12 (2) For the following register, it's internal status after reset is corrected: * Target register: processor mode register 0 (address 5E16) * Correction: the status of bit 1 is "0". (Not "1".) * Related page: page 12 (1/1) |
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